Keywords:
Electronic circuit design-Data processing.
;
Integrated circuits-Computer-aided design.
;
Computational intelligence.
;
Electronic books.
Description / Table of Contents:
This book features recent research on computational intelligence techniques for the automated design of analog and high-frequency circuits. It will help readers handle state-of-the-art algorithms and even design their own methods.
Type of Medium:
Online Resource
Pages:
1 online resource (243 pages)
Edition:
1st ed.
ISBN:
9783642391620
Series Statement:
Studies in Computational Intelligence Series ; v.501
URL:
https://ebookcentral.proquest.com/lib/geomar/detail.action?docID=3092062
DDC:
621.38150285
Language:
English
Note:
Intro -- Preface -- Contents -- 1 Basic Concepts and Background -- 1.1 Introduction -- 1.2 An Introduction into Computational Intelligence -- 1.2.1 Evolutionary Computation -- 1.2.2 Fuzzy Logic -- 1.2.3 Machine Learning -- 1.3 Fundamental Concepts in Optimization -- 1.4 Design and Computer-Aided Design of Analog/RF IC -- 1.4.1 Overview of Analog/RF Circuit and System Design -- 1.4.2 Overview of the Computer-Aided Design of Analog/RF ICs -- 1.5 Summary -- References -- 2 Fundamentals of Optimization Techniques in Analog IC Sizing -- 2.1 Analog IC Sizing: Introduction and Problem Definition -- 2.2 Review of Analog IC Sizing Approaches -- 2.3 Implementation of Evolutionary Algorithms -- 2.3.1 Overview of the Implementation of an EA -- 2.3.2 Differential Evolution -- 2.4 Basics of Constraint Handling Techniques -- 2.4.1 Static Penalty Functions -- 2.4.2 Selection-Based Constraint Handling Method -- 2.5 Multi-objective Analog Circuit Sizing -- 2.5.1 NSGA-II -- 2.5.2 MOEA/D -- 2.6 Analog Circuit Sizing Examples -- 2.6.1 Folded-Cascode Amplifier -- 2.6.2 Single-Objective Constrained Optimization -- 2.6.3 Multi-objective Optimization -- 2.7 Summary -- References -- 3 High-Performance Analog IC Sizing: Advanced Constraint Handling and Search Methods -- 3.1 Challenges in Analog Circuit Sizing -- 3.2 Advanced Constrained Optimization Techniques -- 3.2.1 Overview of the Advanced Constraint Handling Techniques -- 3.2.2 A Self-Adaptive Penalty Function-Based Method -- 3.3 Hybrid Methods -- 3.3.1 Overview of Hybrid Methods -- 3.3.2 Popular Hybridization and Memetic Algorithm for Numerical Optimization -- 3.4 MSOEA: A Hybrid Method for Analog IC Sizing -- 3.4.1 Evolutionary Operators -- 3.4.2 Constraint Handling Method -- 3.4.3 Scaling Up of MSOEA -- 3.4.4 Experimental Results of MSOEA -- 3.5 Summary -- References.
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4 Analog Circuit Sizing with Fuzzy Specifications: Addressing Soft Constraints -- 4.1 Introduction -- 4.2 The Motivation of Analog Circuit Sizing with Imprecise Specifications -- 4.2.1 Why Imprecise Specifications Are Necessary -- 4.2.2 Review of Early Works -- 4.3 Design of Fuzzy Numbers -- 4.4 Fuzzy Selection-Based Constraint Handling Methods (Single-Objective) -- 4.5 Single-Objective Fuzzy Analog IC Sizing -- 4.5.1 Fuzzy Selection-Based Differential Evolution Algorithm -- 4.5.2 Experimental Results and Comparisons -- 4.6 Multi-objective Fuzzy Analog Sizing -- 4.6.1 Multi-objective Fuzzy Selection Rules -- 4.6.2 Experimental Results for Multi-objective Fuzzy Analog Circuit Sizing -- 4.7 Summary -- References -- 5 Process Variation-Aware Analog Circuit Sizing: Uncertain Optimization -- 5.1 Introduction to Analog Circuit Sizing Considering Process Variations -- 5.1.1 Why Process Variations Need to be Taken into Account in Analog Circuit Sizing -- 5.1.2 Yield Optimization, Yield Estimation and Variation-Aware Sizing -- 5.1.3 Traditional Methods for Yield Optimization -- 5.2 Uncertain Optimization Methodologies -- 5.3 The Pruning Method -- 5.4 Advanced MC Sampling Methods -- 5.4.1 AYLeSS: A Fast Yield Estimation Method for Analog IC -- 5.4.2 Experimental Results of AYLeSS -- 5.5 Summary -- References -- 6 Ordinal Optimization-Based Methods for Efficient Variation-Aware Analog IC Sizing -- 6.1 Ordinal Optimization -- 6.2 Efficient Evolutionary Search Techniques -- 6.2.1 Using Memetic Algorithms -- 6.2.2 Using Modified Evolutionary Search Operators -- 6.3 Integrating OO and Efficient Evolutionary Search -- 6.4 Experimental Methods and Verifications of ORDE -- 6.4.1 Experimental Methods for Uncertain Optimization with MC Simulations -- 6.4.2 Experimental Verifications of ORDE.
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6.5 From Yield Optimization to Single-Objective Analog Circuit Variation-Aware Sizing -- 6.5.1 ORDE-Based Single-Objective Variation-Aware Analog Circuit Sizing -- 6.5.2 Example -- 6.6 Bi-objective Variation-Aware Analog Circuit Sizing -- 6.6.1 The MOOLP Algorithm -- 6.6.2 Experimental Results -- 6.7 Summary -- References -- 7 Electromagnetic Design Automation: Surrogate Model Assisted Evolutionary Algorithm -- 7.1 Introduction to Simulation-Based Electromagnetic Design Automation -- 7.2 Review of the Traditional Methods -- 7.2.1 Integrated Passive Component Synthesis -- 7.2.2 RF Integrated Circuit Synthesis -- 7.2.3 Antenna Synthesis -- 7.3 Challenges of Electromagnetic Design Automation -- 7.4 Surrogate Model Assisted Evolutionary Algorithms -- 7.5 Gaussian Process Machine Learning -- 7.5.1 Gaussian Process Modeling -- 7.5.2 Discussions of GP Modeling -- 7.6 Artificial Neural Networks -- 7.7 Summary -- References -- 8 Passive Components Synthesis at High Frequencies: Handling Prediction Uncertainty -- 8.1 Individual Threshold Control Method -- 8.1.1 Motivations and Algorithm Structure -- 8.1.2 Determination of the MSE Thresholds -- 8.2 The GPDECO Algorithm -- 8.2.1 Scaling Up of GPDECO -- 8.2.2 Experimental Verification of GPDECO -- 8.3 Prescreening Methods -- 8.3.1 The Motivation of Prescreening -- 8.3.2 Widely Used Prescreening Methods -- 8.4 MMLDE: A Hybrid Prescreening and Prediction Method -- 8.4.1 General Overview -- 8.4.2 Integrating Surrogate Models into EA -- 8.4.3 The General Framework of MMLDE -- 8.4.4 Experimental Results of MMLDE -- 8.5 SAEA for Multi-objective Expensive Optimization -- 8.5.1 Overview of Multi-objective Expensive Optimization Methods -- 8.5.2 The Generation Control Method -- 8.6 Handling Multiple Objectives in SAEA -- 8.6.1 The GPMOOG Method -- 8.6.2 Experimental Result -- 8.7 Summary -- References.
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9 mm-Wave Linear Amplifier Design Automation: A First Step to Complex Problems -- 9.1 Problem Analysis and Key Ideas -- 9.1.1 Overview of EMLDE -- 9.1.2 The Active Components Library and the Look-up Table for Transmission Lines -- 9.1.3 Handling Cascaded Amplifiers -- 9.1.4 The Two Optimization Loops -- 9.2 Naive Bayes Classification -- 9.3 Key Algorithms in EMLDE -- 9.3.1 The ABGPDE Algorithm -- 9.3.2 The Embedded SBDE Algorithm -- 9.4 Scaling Up of the EMLDE Algorithm -- 9.5 Experimental Results -- 9.5.1 Example Circuit -- 9.5.2 Three-Stage Linear Amplifier Synthesis -- 9.6 Summary -- References -- 10 mm-Wave Nonlinear IC and Complex Antenna Synthesis: Handling High Dimensionality -- 10.1 Main Challenges for the Targeted Problem and Discussions -- 10.2 Dimension Reduction -- 10.2.1 Key Ideas -- 10.2.2 GP Modeling with Dimension Reduction Versus Direct GP Modeling -- 10.3 The Surrogate Model-Aware Search Mechanism -- 10.4 Experimental Tests on Mathematical Benchmark Problems -- 10.4.1 Test Problems -- 10.4.2 Performance and Analysis -- 10.5 60GHz Power Amplifier Synthesis by GPEME -- 10.6 Complex Antenna Synthesis with GPEME -- 10.6.1 Example 1: Microstrip-fed Crooked Cross Slot Antenna -- 10.6.2 Example 2: Inter-chip Wireless Antenna -- 10.6.3 Example 3: Four-element Linear Array Antenna -- 10.7 Summary -- References.
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