In:
MRS Proceedings, Springer Science and Business Media LLC, Vol. 811 ( 2004)
Abstract:
The dielectric breakdown behavior of poly-Si gate CMOSFETs with HfAlOx/SiON gate dielectric fabricated using mass production worthy 300 mm process was investigated. If SiO 2 is used as an interfacial layer (IL), the IL reduction and the intermixing between the HfAlOx layer and the IL occurred, which causes extrinsic breakdown. By using the SiON of [N]=18% as an IL and setting the maximum temperature after the HfAlOx deposition to be 1000°C, the interfacial reaction was suppressed and the extrinsic breakdown component was eliminated. In the case of the n-capacitor accumulation, an abrupt increase of gate lea kage was observed, which is believed to correspond to the IL breakdown. The mean time to failure (MTTF for 0.1cm 2 at 125°C) is long enough. On the other hand, gate current initially decreases and then starts to increase in the case of p-capacitor accumulation. If we define the time to breakdown at the onset of current increase, the MTTF would be only 3.7 years if it obeys the V-plot (MTTF predicted by 1/V-plot was 1.6×10 7 years).
Type of Medium:
Online Resource
ISSN:
0272-9172
,
1946-4274
DOI:
10.1557/PROC-811-D2.7
Language:
English
Publisher:
Springer Science and Business Media LLC
Publication Date:
2004
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