In:
Electronics, MDPI AG, Vol. 8, No. 11 ( 2019-11-07), p. 1307-
Abstract:
This paper demonstrates the design and implementation of an all-digital phase-lockedloop (ADPLL) on Field Programmable Gate Array (FPGA). It is useful as an emulation techniqueto show the feasibility and effectiveness of the ADPLL in the early design stage. A D-S modulator(DSM, Delta-Sigma Modulator)-based digitally controlled ring-oscillator (ring-DCO) design, whichis fully synthesizable in Verilog HDL, is presented. This ring-DCO has fully digital control andfractional tuning range using the DSM. The ring-DCO does not contain library-specific cells andcan be synthesized independently of the standard cell library, thus making the design portable andreducing the time required to fit for different semiconductor processes considerably. Implementedring-DCO has a wide tuning range and high-frequency resolution which meet the demands ofsystem-level integration. The ADPLL implemented in this work has the characteristics of designflexibility, a wide range of working frequency from 120 MHz to 300 MHz, and a fast responsefor achieving a locked state. The proposed ADPLL can be easily ported to different processes ina short time. The design adaptation cost is limited to adjustment of loop parameters in the code.Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable forSystem-on-Chip (SoC) applications.
Type of Medium:
Online Resource
ISSN:
2079-9292
DOI:
10.3390/electronics8111307
Language:
English
Publisher:
MDPI AG
Publication Date:
2019
detail.hit.zdb_id:
2662127-7
