In:
Photonics Research, Optica Publishing Group, Vol. 11, No. 2 ( 2023-02-01), p. 143-
Abstract:
A hybrid integrated 16-channel silicon transmitter based on co-designed photonic integrated circuits (PICs) and electrical chiplets is demonstrated. The driver in the 65 nm CMOS process employs the combination of a distributed architecture, two-tap feedforward equalization (FFE), and a push–pull output stage, exhibiting an estimated differential output swing of 4.0 V pp . The rms jitter of 2.0 ps is achieved at 50 Gb/s under nonreturn-to-zero on–off keying (NRZ-OOK) modulation. The PICs are fabricated on a standard silicon-on-insulator platform and consist of 16 parallel silicon dual-drive Mach–Zehnder modulators on a single chip. The chip-on-board co-packaged Si transmitter is constituted by the multichannel chiplets without any off-chip bias control, which significantly simplifies the system complexity. Experimentally, the open and clear optical eye diagrams of selected channels up to 50 Gb/s OOK with extinction ratios exceeding 3 dB are obtained without any digital signal processing. The power consumption of the Si transmitter with a high integration density featuring a throughput up to 800 Gb/s is only 5.35 pJ/bit, indicating a great potential for massively parallel terabit-scale optical interconnects for future hyperscale data centers and high-performance computing systems.
Type of Medium:
Online Resource
ISSN:
2327-9125
Language:
English
Publisher:
Optica Publishing Group
Publication Date:
2023
detail.hit.zdb_id:
2724783-1
