In:
Japanese Journal of Applied Physics, IOP Publishing, Vol. 49, No. 12R ( 2010-12-01), p. 121501-
Abstract:
A 0.5 V six-transistor static random access memory (6T-SRAM) with ferroelectric-gate field-effect-transistors (Fe-FETs) is proposed and experimentally demonstrated for the first time. During the read and the hold, the threshold voltage ( V TH ) of Fe-FETs automatically changes to increase the static noise margin (SNM) by 60%. During the stand-by, the V TH of the proposed SRAM cell increases to decrease the leakage current by 42%. In case of the read, the V TH of the read transistor decreases and increases the cell read current to achieve the fast read. During the write, the V TH of the SRAM cell dynamically changes and assist the cell data to flip, realizing a write assist function. The enlarged SNM realizes the V DD reduction by 0.11 V, which decreases the active power by 32%. The proposed SRAM layout is the same as the conventional 6T-SRAM and there is no area penalty.
Type of Medium:
Online Resource
ISSN:
0021-4922
,
1347-4065
DOI:
10.1143/JJAP.49.121501
Language:
Unknown
Publisher:
IOP Publishing
Publication Date:
2010
detail.hit.zdb_id:
218223-3
detail.hit.zdb_id:
797294-5
detail.hit.zdb_id:
2006801-3
detail.hit.zdb_id:
797295-7
