In:
Japanese Journal of Applied Physics, IOP Publishing, Vol. 30, No. 11S ( 1991-11-01), p. 3178-
Abstract:
The processes used for the surface planarization of the interlevel dielectrics which is one of the major problems of the multilevel interconnection CMOS technology, are becoming increasingly sophisticated. As a consequence, the reproducibility of the total process requires an accurate control of these technics in order to increase die yields. The DOPED method, developed for a non-contact on-line monitoring of flow annealing of BPSG films has been applied to the “cold” planarization techniques implemented in the CNET 0.7 µm technology. Results are obtained for TEOS deposition and etchback techniques and SOG total etchback.
Type of Medium:
Online Resource
ISSN:
0021-4922
,
1347-4065
DOI:
10.1143/JJAP.30.3178
Language:
Unknown
Publisher:
IOP Publishing
Publication Date:
1991
detail.hit.zdb_id:
218223-3
detail.hit.zdb_id:
797294-5
detail.hit.zdb_id:
2006801-3
detail.hit.zdb_id:
797295-7
