In:
International Journal of Nanoscience, World Scientific Pub Co Pte Ltd, Vol. 11, No. 04 ( 2012-08), p. 1240024-
Abstract:
This work presents a nanodamascene process for a CMOS back-end-of-line fabrication of metallic single electron transistor(SET), together with the use of simulation tools for the development of a SET SRAM memory cell. We show room temperature electrical characterizations of SETs fabricated on CMOS with relaxed dimensions, and simulations of a SET SRAM memory cell. Using their physical characteristics achievable through the use of atomic layer deposition, it will be demonstrated that it has the potential to operate at temperature up to 398 K, and that power consumption is less than that of equivalent circuit in advanced CMOS technologies. In order to take advantage of both low power SETs and high CMOS drive efficiency, a hybrid 3D SET CMOS circuit is proposed.
Type of Medium:
Online Resource
ISSN:
0219-581X
,
1793-5350
DOI:
10.1142/S0219581X12400248
Language:
English
Publisher:
World Scientific Pub Co Pte Ltd
Publication Date:
2012
SSG:
11