In:
Proceedings, annual meeting, Electron Microscopy Society of America, Cambridge University Press (CUP), Vol. 48, No. 4 ( 1990-08), p. 564-565
Abstract:
Continuing increase in integration density requires reduction of minimum feature sizes which have reached a level of 0.8 μm for the 4 Megabit dynamic random access memory (DRAM) and are approaching about 0.5 μm for the next generation DRAMs. The thickness of thin dielectrics will be in the nanometer range. Besides the dimensions of the small device structures also the properties of all involved materials have to be controlled carefully. Due to its capability of providing high-resolution imaging and analytical information material characterization by cross-sectional TEM is getting increasingly important during process development. Several examples related to various process steps will be presented. For the trench capacitor in 4 Mbit DRAMs thin dielectrics consisting of an SiO 2 -Si 3 N 4 -SiO 2 triple layer are employed. While the thickness of the bottom oxide is reduced at the upper trench edge the nitride layer coats this edge uniformly since it is deposited from the vapor phase (Fig.1a). For the capacitor in a 64 Mbit memory cell oxide thicknesses of about 2 nm and 5 nm for the nitride will be required (Fig.1b).
Type of Medium:
Online Resource
ISSN:
0424-8201
,
2690-1315
DOI:
10.1017/S0424820100175958
Language:
English
Publisher:
Cambridge University Press (CUP)
Publication Date:
1990
SSG:
11
