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Metastability-Induced TRNG Architecture on FPGA

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Abstract

Due to the emerging high-speed digital infrastructure, the protection of data being shared throughout the open networks has been a challenging task. By large, the dependency on cryptographic primitives exists to encounter cyberspace challenges. Key generation is a core process of any cryptographic application which improvises the strength of the algorithm. Reconfigurable hardware-assisted true random number generators (TRNGs) play a crucial role in key generation to provide high-speed cryptographic solutions. In this work, metastability-influenced TRNG architecture on Altera Cyclone II EP2C20F484C7 FPGA has been proposed. The 256 units of SR latches with de-synchronisation technique were the prime source used to harvest the true randomness. TRNG design consumed 1851 logic elements with a dynamic power dissipation of 4.41 mW. Proposed architecture achieves a high throughput of 26.64065 Mbps using 27 MHz onboard sampling clock. This TRNG has been validated through entropy, correlation, NIST SP 800-22 batteries of test, linear complexity test, restart experiment and hamming distance analysis.

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Acknowledgements

The authors wish to thank SASTRA Deemed University for providing the infrastructure through the Research & Modernization Fund (Ref. No. R&M/0026/SEEE-010/2012-13) to carry out the research work.

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Authors and Affiliations

  1. School of EEE, SASTRA Deemed University, Thanjavur, Tamilnadu, India

    R. Sivaraman, Sundararaman Rajagopalan, A. Sridevi, J. B. B. Rayappan & Amirtharajan Rengarajan

  2. Cyber Security and Risk Services, Wipro Technologies Ltd., Bangalore, India

    Moorthi Paramasivam Vijaya Annamalai

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  1. R. Sivaraman
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  2. Sundararaman Rajagopalan
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  5. Moorthi Paramasivam Vijaya Annamalai
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Correspondence to Amirtharajan Rengarajan.

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Sivaraman, R., Rajagopalan, S., Sridevi, A. et al. Metastability-Induced TRNG Architecture on FPGA. Iran J Sci Technol Trans Electr Eng 44, 47–57 (2020). https://doi.org/10.1007/s40998-019-00234-2

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