Abstract
We clarified that the fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel "double titanium deposited silicide (DTD)" process has been developed. The key point of this process is the deposition and subsequent removal of dummy titanium before silicidation. Contaminated silicon and gate poly-silicon surface layer caused by reactive ion etching was removed perfectly and an ultra-clean surface was obtained. As a result, low sheet resistance (3 Ω/\Box) was obtained in both n+ and p+ very fine 0.1 µm gates.