An 8-bit 5-Gsample/s Time-Interleaved Analog-to-Digital Converter Used for Optical Communication

Yu Han Gao; Yong Lu Wang; Guang Bin Chen; Zheng Ping Zhang; Can Zhu; Lei Zhang; Rong Ke Ye; Rong Bin Hu

doi:10.4028/www.scientific.net/AMR.756-759.205

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 756-759An 8-bit 5-Gsample/s Time-Interleaved...

An 8-bit 5-Gsample/s Time-Interleaved Analog-to-Digital Converter Used for Optical Communication

Abstract:

In this paper, we present an 8-bit 5 Gsample/s time-interleaved analog-to-digital converter (TI ADC). A 4-phase low jitter clock is designed to control four 1.25 Gsample/s sub-ADCs which is implemented using folding and interpolating architecture. Digital calibration is used to adjust the offset error and gain error of sub-ADCs. Meanwhile, serial peripheral interface (SPI) is adopted to adjust mismatch of gain and sample time between sub-ADCs. The whole TI ADC is designed using a 0.18m SiGe BiCMOS process. The whole ADC has a SNR of about 45 dB at the input frequency of 495 MHZ and an equivalent ENOB of 7.2 bits.

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Periodical:

Advanced Materials Research (Volumes 756-759)

Pages:

205-208

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.756-759.205

Citation:

Cite this paper

Online since:

September 2013

Authors:

Yu Han Gao, Yong Lu Wang, Guang Bin Chen, Zheng Ping Zhang, Can Zhu, Lei Zhang, Rong Ke Ye, Rong Bin Hu

Keywords:

ADC, Digital Calibration, Folding, Interpolate, SNR, SPI, Time-Interleaved

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References

[1] A. Barna, D.I. Porat, Integrated Circuits in Digital Electronics (Wiley, New York, 1973).

Google Scholar

[2] A.G.F. Dingwall, Monolithic expandable 6 bit 20 MHz CMOS/SOS A/D converter. IEEE J. Solid-State Circuits 14(6), 926–932 (1979).

DOI: 10.1109/jssc.1979.1051299

Google Scholar

[3] W.C. Black, D.A. Hodges, Time interleaved converter arrays. IEEE J. Solid-State Circuits15(6), 1022–1029 (1980).

DOI: 10.1109/jssc.1980.1051512

Google Scholar

[4] Zhang Zhengping. etc. An ultra high-speed 8-bit timing interleave folding & interpolating analog-to-digital converter with digital foreground calibration technology. Journal of Semiconductors, Vol. 32, No. 9, (2011).

DOI: 10.1088/1674-4926/32/9/095010

Google Scholar