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  • 1
    Online-Ressource
    Online-Ressource
    Association for Computing Machinery (ACM) ; 2002
    In:  ACM SIGARCH Computer Architecture News Vol. 30, No. 2 ( 2002-05), p. 123-134
    In: ACM SIGARCH Computer Architecture News, Association for Computing Machinery (ACM), Vol. 30, No. 2 ( 2002-05), p. 123-134
    Kurzfassung: We develop an availability solution, called SafetyNet, that uses a unified, lightweight checkpoint/recovery mechanism to support multiple long-latency fault detection schemes. At an abstract level, SafetyNet logically maintains multiple, globally consistent checkpoints of the state of a shared memory multiprocessor (i.e., processors, memory, and coherence permissions), and it recovers to a pre-fault checkpoint of the system and re-executes if a fault is detected. SafetyNet efficiently coordinates checkpoints across the system in logical time and uses "logically atomic" coherence transactions to free checkpoints of transient coherence state. SafetyNet minimizes performance overhead by pipelining checkpoint validation with subsequent parallel execution.We illustrate SafetyNet avoiding system crashes due to either dropped coherence messages or the loss of an interconnection network switch (and its buffered messages). Using full-system simulation of a 16-way multiprocessor running commercial workloads, we find that SafetyNet (a) adds statistically insignificant runtime overhead in the common-case of fault-free execution, and (b) avoids a crash when tolerated faults occur.
    Materialart: Online-Ressource
    ISSN: 0163-5964
    RVK:
    Sprache: Englisch
    Verlag: Association for Computing Machinery (ACM)
    Publikationsdatum: 2002
    ZDB Id: 2088489-8
    ZDB Id: 186012-4
    Standort Signatur Einschränkungen Verfügbarkeit
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  • 2
    In: Theoretical Computer Science, Elsevier BV, Vol. 894 ( 2021-11), p. 50-78
    Materialart: Online-Ressource
    ISSN: 0304-3975
    RVK:
    Sprache: Englisch
    Verlag: Elsevier BV
    Publikationsdatum: 2021
    ZDB Id: 193706-6
    ZDB Id: 1466347-8
    Standort Signatur Einschränkungen Verfügbarkeit
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  • 3
    Online-Ressource
    Online-Ressource
    Association for Computing Machinery (ACM) ; 2003
    In:  ACM SIGARCH Computer Architecture News Vol. 31, No. 2 ( 2003-05), p. 206-217
    In: ACM SIGARCH Computer Architecture News, Association for Computing Machinery (ACM), Vol. 31, No. 2 ( 2003-05), p. 206-217
    Kurzfassung: Destination-set prediction can improve the latency/bandwidth tradeoff in shared-memory multiprocessors. The destination set is the collection of processors that receive a particular coherence request. Snooping protocols send requests to the maximal destination set (i.e., all processors), reducing latency for cache-to-cache misses at the expense of increased traffic. Directory protocols send requests to the minimal destination set, reducing bandwidth at the expense of an indirection through the directory for cache-to-cache misses. Recently proposed hybrid protocols trade-off latency and bandwidth by directly sending requests to a predicted destination set.This paper explores the destination-set predictor design space, focusing on a collection of important commercial workloads. First, we analyze the sharing behavior of these workloads. Second, we propose predictors that exploit the observed sharing behavior to target different points in the latency/bandwidth tradeoff. Third, we illustrate the effectiveness of destination-set predictors in the context of a multicast snooping protocol. For example, one of our predictors obtains almost 90% of the performance of snooping while using only 15% more bandwidth than a directory protocol (and less than half the bandwidth of snooping).
    Materialart: Online-Ressource
    ISSN: 0163-5964
    RVK:
    Sprache: Englisch
    Verlag: Association for Computing Machinery (ACM)
    Publikationsdatum: 2003
    ZDB Id: 2088489-8
    ZDB Id: 186012-4
    Standort Signatur Einschränkungen Verfügbarkeit
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  • 4
    Online-Ressource
    Online-Ressource
    Association for Computing Machinery (ACM) ; 2005
    In:  ACM SIGARCH Computer Architecture News Vol. 33, No. 4 ( 2005-11), p. 92-99
    In: ACM SIGARCH Computer Architecture News, Association for Computing Machinery (ACM), Vol. 33, No. 4 ( 2005-11), p. 92-99
    Kurzfassung: The Wisconsin Multifacet Project has created a simulation toolset to characterize and evaluate the performance of multiprocessor hardware systems commonly used as database and web servers. We leverage an existing full-system functional simulation infrastructure (Simics [14]) as the basis around which to build a set of timing simulator modules for modeling the timing of the memory system and microprocessors. This simulator infrastructure enables us to run architectural experiments using a suite of scaled-down commercial workloads [3] . To enable other researchers to more easily perform such research, we have released these timing simulator modules as the Multifacet General Execution-driven Multiprocessor Simulator (GEMS) Toolset, release 1.0, under GNU GPL [9].
    Materialart: Online-Ressource
    ISSN: 0163-5964
    RVK:
    Sprache: Englisch
    Verlag: Association for Computing Machinery (ACM)
    Publikationsdatum: 2005
    ZDB Id: 2088489-8
    ZDB Id: 186012-4
    Standort Signatur Einschränkungen Verfügbarkeit
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  • 5
    Online-Ressource
    Online-Ressource
    Association for Computing Machinery (ACM) ; 2000
    In:  ACM SIGARCH Computer Architecture News Vol. 28, No. 5 ( 2000-12), p. 25-36
    In: ACM SIGARCH Computer Architecture News, Association for Computing Machinery (ACM), Vol. 28, No. 5 ( 2000-12), p. 25-36
    Kurzfassung: Symmetric muultiprocessor (SMP) servers provide superior performance for the commercial workloads that dominate the Internet. Our simulation results show that over one-third of cache misses by these applications result in cache-to-cache transfers, where the data is found in another processor's cache rather than in memory. SMPs are optimized for this case by using snooping protocols that broadcast address transactions to all processors. Conversely, directory-based shared-memory systems must indirectly locate the owner and sharers through a directory, resulting in larger average miss latencies.This paper proposes timestamp snooping, a technique that allows SMPs to i) utilize high-speed switched interconnection networks and ii) exploit physical locality by delivering address transactions to processors and memories without regard to order. Traditional snooping requires physical ordering of transactions. Timestamp snooping works by processing address transactions in a logical order. Logical time is maintained by adding a few bits per address transaction and having network switches perform a handshake to ensure on-time delivery. Processors and memories then reorder transactions based on their timestamps to establish a total order.We evaluate timestamp snooping with commercial workloads on a 16-processor SPARC system using the Simics full-system simulator. We simulate both an indirect (butterfly) and a direct (torus) network design. For OLTP, DSS, web serving, web searching, and one scientific application, timestamp snooping with the butterfly network runs 6-28% faster than directories, at a cost of 13-43% more link traffic. Similarly, with the torus network, timestamp snooping runs 6-29% faster for 17-37% more link traffic. Thus, timestamp snooping is worth considering when buying more interconnect bandwidth is easier than reducing interconnect latency.
    Materialart: Online-Ressource
    ISSN: 0163-5964
    RVK:
    Sprache: Englisch
    Verlag: Association for Computing Machinery (ACM)
    Publikationsdatum: 2000
    ZDB Id: 2088489-8
    ZDB Id: 186012-4
    Standort Signatur Einschränkungen Verfügbarkeit
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  • 6
    Online-Ressource
    Online-Ressource
    Association for Computing Machinery (ACM) ; 2003
    In:  ACM SIGARCH Computer Architecture News Vol. 31, No. 2 ( 2003-05), p. 182-193
    In: ACM SIGARCH Computer Architecture News, Association for Computing Machinery (ACM), Vol. 31, No. 2 ( 2003-05), p. 182-193
    Kurzfassung: Many future shared-memory multiprocessor servers will both target commercial workloads and use highly-integrated "glueless" designs. Implementing low-latency cache coherence in these systems is difficult, because traditional approaches either add indirection for common cache-to-cache misses (directory protocols) or require a totally-ordered interconnect (traditional snooping protocols). Unfortunately, totally-ordered interconnects are difficult to implement in glueless designs. An ideal coherence protocol would avoid indirections and interconnect ordering; however, such an approach introduces numerous protocol races that are difficult to resolve.We propose a new coherence framework to enable such protocols by separating performance from correctness. A performance protocol can optimize for the common case (i.e., absence of races) and rely on the underlying correctness substrate to resolve races, provide safety, and prevent starvation. We call the combination Token Coherence, since it explicitly exchanges and counts tokens to control coherence permissions.This paper develops TokenB, a specific Token Coherence performance protocol that allows a glueless multiprocessor to both exploit a low-latency unordered interconnect (like directory protocols) and avoid indirection (like snooping protocols). Simulations using commercial workloads show that our new protocol can significantly outperform traditional snooping and directory protocols.
    Materialart: Online-Ressource
    ISSN: 0163-5964
    RVK:
    Sprache: Englisch
    Verlag: Association for Computing Machinery (ACM)
    Publikationsdatum: 2003
    ZDB Id: 2088489-8
    ZDB Id: 186012-4
    Standort Signatur Einschränkungen Verfügbarkeit
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