In:
Japanese Journal of Applied Physics, IOP Publishing, Vol. 50, No. 4S ( 2011-04-01), p. 04DC06-
Abstract:
This paper reports novel, non-epitaxial raised source/drain (S/D) approaches to decrease the parasitic external resistance in complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs) fabricated on ultrathin silicon on insulator (UTSOI). This technique utilizes a metal Schottky S/D process with dopant segregation. Selectively formed NiSi 2 with dopant segregation fabricated by laser-spike annealing (LSA) significantly lowered effective Shottky-barrier height and, thereby, lowered contact resistance (ρ c ). Satisfying the requirements of UTSOI MOSFETs in the 32-nm node for low stand-by power (LSTP) application, external parasitic resistance was reduced to 140 (NMOS) and 350 (PMOS) Ω µm. Our results show that ρ c is an important component of parasitic resistance in terms of improving device performance of UTSOI MOSFETs.
Type of Medium:
Online Resource
ISSN:
0021-4922
,
1347-4065
DOI:
10.1143/JJAP.50.04DC06
Language:
Unknown
Publisher:
IOP Publishing
Publication Date:
2011
detail.hit.zdb_id:
218223-3
detail.hit.zdb_id:
797294-5
detail.hit.zdb_id:
2006801-3
detail.hit.zdb_id:
797295-7
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