In:
ECS Meeting Abstracts, The Electrochemical Society, Vol. MA2023-01, No. 33 ( 2023-08-28), p. 1872-1872
Abstract:
Nanowire transistors constitute an alternative for the continuous downscaling of MOSFETs. These devices present a trigate architecture featuring the fin width (W FIN ) and height (H FIN ) with similar dimensions, in the order of tenths of nanometers [1], which improves the gate control on the channel charges, reducing short-channel effects (SCE) and improves electrical properties in both digital and analog applications [1] . Junctionless nanowire transistors (JL) are easier to fabricate than inversion-mode MOSFETs [2]. They also are less vulnerable to the occurrence of SCE, which is one of the main concerns when downscaling the MOS transistor [3, 4] . Unlike inversion mode (IM) transistors, the junctionless device is made with a heavily doped silicon layer with the same doping type from source to drain [2, 5]. To lower the series resistance, the source and drain receive an additional doping step to increase their concentration. Although JL transistors are a good alternative for the continuous downscaling of MOS transistors, they still have their basic operation like any other transistor MOSFET. Therefore, it is not completely immune from SCE, such as Drain-Induced Barrier Lowering (DIBL) effect. In this work, a comparison between the DIBL effect in junctionless and inversion-mode nanowire transistors is performed. Experimental results at room and high temperatures are presented for devices with different channel widths. The JL and IM nanowire transistors used in this work were fabricated at CEA-Leti, as described in reference [6]. Devices with 10 parallel channels and channel length (L) of 40 nm and 100 nm were measured, fin width (W FIN ) of 12 nm, 17 nm, 22 nm, and 42 nm. Two different values of drain voltage (V D ) were applied for all devices, V D1 = 40 mV and V D2 = 800 mV. Finally, the DIBL has been calculated as DIBL=|V T2 – V T1 | /(V D2 – V D1 ). The threshold voltage in both V D has been extracted as described in ref. [7]. The analysis for DIBL as a function of fin width is shown in Figure 1(A). For devices with L=100nm, no SCE has been observed and all devices present Subthreshold Slope (SS) close to the theoretical limit. Also, for W FIN up to 22 nm, DIBL is the same both for IM and JL nanowires. When downscaling the length to 40 nm, despite of DIBL increase for all devices, no degradation on SS is seen for JL, whereas IM devices exhibit SS 〉 82mV/dec. Considering reasonable characteristics, i.e., DIBL=100mV/V and S=80 mV/dec [8], except from W FIN =42nm, all JL devices meet these requirements, whereas no IM nanowire with L=40 nm could be used. Even if maximum allowable DIBL were increased to 120mV/V, only the narrowest IM with L=40nm would be acceptable. Aiming to verify the influence of the temperature on the DIBL, Figure 1(B) shows the variation of DIBL in relation to room temperature for IM and JL nanowires with L=100nm and W FIN =12nm, which have similar DIBL at 300K. One can see that DIBL variation with temperature in the IM device is larger than in JL. While the IM transistor presented a DIBL variation of 0.15(mV/V)/K, for the JL one, it is 0.11(mV/V)/K. These results indicate that apart from the good immunity to SCE, JL nanowires are less susceptible to DIBL variation with temperature. Acknowledgements The authors thank financial support from CAPES, CNPq and FAPESP. References [1] T. A. Oproglidis, T. A. Karatsori, S. Barraud, G. Ghibaudo and C. A. Dimitriadis, Effect of Temperature on the Performance of Triple-Gate Junctionless Transistors, in IEEE Transactions on Electron Devices , vol.65, no.8, pp.3562-3566, 2018. [2] J.-P. Colinge et al, Junctionless Nanowire Transistor (JNT): Properties and design guidelines, Solid-State Electronics, Volumes 65–66, 2011, Pages 33-37. [3] J.-P. Colinge, Junctionless transistors, 2012 IEEE International Meeting for Future of Electron Devices, Kansai, 2012, pp. 1-2. [4] M. Ehteshamuddin, Sajad A. Loan and M. Rafat, Excellent DIBL Immunity in Junctionless Transistor on a High -k Buried, 2017 14th IEEE India Council International Conference (INDICON). [5] T. A. Ribeiro, M. A. Pavanello, Analysis of the electrical parameters of SOI junctionless nanowire transistors at high temperatures, Journal of the Electron Devices Society, April 2021. [6] D. Bosch et al., All-Operation-Regime Characterization and Modeling of Drain Current Variability in Junctionless and Inversion-Mode FDSOI Transistors, 2020 IEEE Symposium on VLSI Technology, 2020, pp. 1-2. [7] M. De Souza et al, Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors, ESSDERC 2021, pp. 223-226, 2021. [8] J.-W. Yang and J. G. Fossum, On the feasibility of nanoscale triple-gate CMOS transistors, in IEEE Transactions on Electron Devices, vol. 52, no. 6, pp. 1159-1164, June 2005. Figure 1
Type of Medium:
Online Resource
ISSN:
2151-2043
DOI:
10.1149/MA2023-01331872mtgabs
Language:
Unknown
Publisher:
The Electrochemical Society
Publication Date:
2023
detail.hit.zdb_id:
2438749-6
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