In:
ACM SIGPLAN Notices, Association for Computing Machinery (ACM), Vol. 46, No. 5 ( 2011-04-11), p. 151-160
Abstract:
In this paper, we propose a data partitioning technique for the memory subsystem that consists of a multi-ported scratchpad memory (SPM) unit and a single-ported data cache in coarse-grained reconfigurable arrays (CGRA) architecture. The embedded reconfigurable processor executes programs by switching between the Non-VLIW and VLIW modes depending on the type of the code region to achieve high performance. The VLIW mode exploits code regions with high ILP that require high memory bandwidth and the Non-VLIW mode exploits those with low ILP that require low memory latency. Our data partitioning technique between the SPM and the data cache is based on data interference graph reduction and profiling information. Given an SPM size, it finds the optimal data partitions by taking the VLIW instruction schedule into consideration. We evaluate our data partitioning technique for the CGRA architecture with three representative multimedia applications.
Type of Medium:
Online Resource
ISSN:
0362-1340
,
1558-1160
DOI:
10.1145/2016603.1967699
Language:
English
Publisher:
Association for Computing Machinery (ACM)
Publication Date:
2011
detail.hit.zdb_id:
2079194-X
detail.hit.zdb_id:
282422-X
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