In:
International Journal of Engineering and Advanced Technology, Blue Eyes Intelligence Engineering and Sciences Engineering and Sciences Publication - BEIESP, Vol. 9, No. 1 ( 2019-10-30), p. 418-423
Abstract:
Universal interconnection networks are prime performance tailback for high performance SoCs (Systems-on-Chip). Since shrinking the size of the ICs (Integrated Circuits) is the main aim, NoC (Network-on-Chip), being a segmental and mountable design tactic is a propitious substitute to outmoded bus-mode architectures. NoC combined with 3D-Routers and label switching technique can guarantee low power consumption, QoS along with less latency. In the proposed work, 3D NoCs are proven to be more advantageous by achieving 39.9% reduction in Area, 1.7% reduction in Power Consumption, and 11.3% reduction in Memory usage.
Type of Medium:
Online Resource
ISSN:
2249-8958
DOI:
10.35940/ijeat.2249-8958
DOI:
10.35940/ijeat.A9407.109119
Language:
Unknown
Publisher:
Blue Eyes Intelligence Engineering and Sciences Engineering and Sciences Publication - BEIESP
Publication Date:
2019
Permalink