In:
Japanese Journal of Applied Physics, IOP Publishing, Vol. 39, No. 4S ( 2000-04-01), p. 2098-
Abstract:
A 0.25-µm ferroelectric memory with 16 kbit-cell array was
fabricated. A Pb(Zr, Ti)O 3 (PZT) capacitor was formed on a
metal(Al)/via(W)-stacked plug using low temperature metal organic chemical vapor deposition (MO-CVD). The backend process had no
effect on the PZT capacitor properties. The 1×1 µm 2 capacitor shows good fatigue and imprint
endurance. Signal voltage on the bit-line in the cell array is 1.06 V for switching and 0.58 V for unswitching. These results
agree well with the pulse-response measurement of the parallel capacitor. However, the signal voltage deviation becomes larger with
the capacitor size reduction. The 16 kbit-cell array shows the column access time of 50 ns and the minimum operation voltage of
1.6 V.
Type of Medium:
Online Resource
ISSN:
0021-4922
,
1347-4065
DOI:
10.1143/JJAP.39.2098
Language:
Unknown
Publisher:
IOP Publishing
Publication Date:
2000
detail.hit.zdb_id:
218223-3
detail.hit.zdb_id:
797294-5
detail.hit.zdb_id:
2006801-3
detail.hit.zdb_id:
797295-7
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