In:
Japanese Journal of Applied Physics, IOP Publishing, Vol. 39, No. 2R ( 2000-02-01), p. 387-
Abstract:
Deep submicron dual-gate metal-oxide-semiconductor field-effect transistors
(MOSFETs) with partially elevated source/drain (S/D) structures were fabricated using complementary MOS (CMOS) technologies. In comparison with well-defined conventional
MOSFETs, it is revealed that the drivability is appreciably enhanced by the S/D elevation and, further, that a p-channel MOSFET gains more from the S/D elevation than
an n-channel MOSFET. Investigation of the parasitic resistance is consistent with the results of the transistor characteristics.
Type of Medium:
Online Resource
ISSN:
0021-4922
,
1347-4065
Language:
Unknown
Publisher:
IOP Publishing
Publication Date:
2000
detail.hit.zdb_id:
218223-3
detail.hit.zdb_id:
797294-5
detail.hit.zdb_id:
2006801-3
detail.hit.zdb_id:
797295-7
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