In:
ACM Transactions on Design Automation of Electronic Systems, Association for Computing Machinery (ACM), Vol. 16, No. 1 ( 2010-11), p. 1-29
Abstract:
This article presents several scan-cell reordering techniques to reduce the signal transitions during the test mode while preserving the don’t-care bits in the test patterns for a later optimization. Combined with a pattern-filling technique, the proposed scan-cell reordering techniques can utilize both high response correlations and pattern correlations to simultaneously minimize scan-out and scan-in transitions. Those scan-shift transitions can be further reduced by selectively using the inverse connections between scan cells. In addition, the trade-off between routing overhead and power consumption can also be controlled by the proposed scan-cell reordering techniques. A series of experiments are conducted to demonstrate the effectiveness of each of the proposed techniques individually.
Type of Medium:
Online Resource
ISSN:
1084-4309
,
1557-7309
DOI:
10.1145/1870109.1870119
Language:
English
Publisher:
Association for Computing Machinery (ACM)
Publication Date:
2010
detail.hit.zdb_id:
1501152-5
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