In:
Journal of Applied Physics, AIP Publishing, Vol. 110, No. 4 ( 2011-08-15)
Abstract:
We present a theoretical and experimental investigation of the recently reported new architecture of a patterned electrode vertical field effect transistor (PE-VFET). The investigation focuses on the role of the embedded source electrode architecture in the device behavior. Current-voltage characteristics was unraveled through the use of a self-consistent numerical simulation resulting in guidelines for the PE-VFET architecture regarding the On/Off current ratio, output current density, and apparent threshold voltage. Current modulation characteristics are obtained through the formation of virtual contacts at the PE nano-features (i.e., perforations) under gate bias, which lead to the formation of vertical channels under drain bias. As the vertical channel is formed the device characteristics change from contact-limited to space-charge-limited. The analytical model strength is shown with the parameter extraction procedure applied to a measured PE-VFET device fabricated using block copolymer lithography and with the appropriate simulation results.
Type of Medium:
Online Resource
ISSN:
0021-8979
,
1089-7550
Language:
English
Publisher:
AIP Publishing
Publication Date:
2011
detail.hit.zdb_id:
220641-9
detail.hit.zdb_id:
3112-4
detail.hit.zdb_id:
1476463-5
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