In:
Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT), IMAPS - International Microelectronics Assembly and Packaging Society, Vol. 2013, No. DPC ( 2013-01-01), p. 001846-001969
Abstract:
In this century, the IC packaging technology continues to make progress at astounding rate to meet the increasing requirements in many fields[1]. High density packaging is normally achieved by using various chip and/or package staking. Due to itsunique bending characteristics, flex substrate has become an ideal candidate for high density 3D packaging, especially applied for the packaging of medical products[2,3] . In this paper, we focus on the process development details of a flexible package, and investigate the main reliability problems through a series of reliability tests. There were three chips in the 3D flexible packaging structure used in our experiments. The center chip had a larger size of 5.95à —4.35mm2, while the edge ones were smaller and had the same size of 1.95à —1.95mm2. The thickness of all the three chips was the same, 200ÃŽ ¼m. All the chips had daisy chain testing structure. The ball diameter and pitch of the bumps were 250ÃŽ ¼m and 400ÃŽ ¼m, respectively. The substrate was a double-layer non-gel flexible substrate, which had polyimide as the core material (dielectric constantâ ‰ ˆ4). The substrate had a dimension of 16.9mmà —5.5mm2, and a total thickness of 80ÃŽ ¼m. Differential transmission line and DC test pads were designed in the testing circuit for high frequency signal and DC electric test. The dimension of the 3D package after folding was about 6à —6.6à —1.3mm3. The assembly process flow is as follows: All the chips were connected to a flexible substrate by using flip-chip bonding process. After underfilling was applied and cured, the two edge chips were folded and stacked onto the center chip. Then encapsulation and BGA ball dropping were followed. By flexible folding and chip stacking, the overall package size was reduced. We chose an epoxy based material as underfilling and encapsulation. X-ray check and c-scan test showed that the encapsulation had no voids in most samples. Autoclave (RH 95%, 125Ã’ °C, 96 hours) and multireflow (260â „ ƒ for 5 times) test were designed to assess the flexible structure and check the package reliability. Electrical measurements were performed to monitor and check the REL output. Some of the important electrical test results are summarized below: (1) After the multireflow test, some of the 2D unfolding samples showed open circuit in DC test, especially around the vicinity of the larger chip in the center. The DC test results of 3D samples showed no significant change after multireflow, while cross-section image showed no delamination in these area. (2) After the autoclave test, open circuit could be observed in most 2D unfolding samples near the region of the larger chip in the center, while open circuit could be seen in some smaller chip region too. For the other good parts, resistance showed an increase of 150–200% than before. The DC test results of 3D samples showed no significant change after autoclave, and the cross-section image showed no delamination in these area. (3) It could be presumed that the center region of the large chip was the weakest link of this package. 3D folding and encapsulation had reinforcement action on the flexible substrate.
Type of Medium:
Online Resource
ISSN:
2380-4491
DOI:
10.4071/2013DPC-tha13
Language:
English
Publisher:
IMAPS - International Microelectronics Assembly and Packaging Society
Publication Date:
2013
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