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  • 1
    Online Resource
    Online Resource
    Universitatsbibliothek der Ruhr-Universitat Bochum ; 2020
    In:  IACR Transactions on Cryptographic Hardware and Embedded Systems ( 2020-08-26), p. 309-336
    In: IACR Transactions on Cryptographic Hardware and Embedded Systems, Universitatsbibliothek der Ruhr-Universitat Bochum, ( 2020-08-26), p. 309-336
    Abstract: Reverse engineering of integrated circuits, i.e., understanding the internals of Integrated Circuits (ICs), is required for many benign and malicious applications. Examples of the former are detection of patent infringements, hardware Trojans or Intellectual Property (IP)-theft, as well as interface recovery and defect analysis, while malicious applications include IP-theft and finding insertion points for hardware Trojans. However, regardless of the application, the reverse engineer initially starts with a large unstructured netlist, forming an incomprehensible sea of gates.This work presents DANA, a generic, technology-agnostic, and fully automated dataflow analysis methodology for flattened gate-level netlists. By analyzing the flow of data between individual Flip Flops (FFs), DANA recovers high-level registers. The key idea behind DANA is to combine independent metrics based on structural and control information with a powerful automated architecture. Notably, DANA works without any thresholds, scenario-dependent parameters, or other “magic” values that the user must choose. We evaluate DANA on nine modern hardware designs, ranging from cryptographic co-processors, over CPUs, to the OpenTitan, a stateof- the-art System-on-Chip (SoC), which is maintained by the lowRISC initiative with supporting industry partners like Google and Western Digital. Our results demonstrate almost perfect recovery of registers for all case studies, regardless whether they were synthesized as FPGA or ASIC netlists. Furthermore, we explore two applications for dataflow analysis: we show that the raw output of DANA often already allows to identify crucial components and high-level architecture features and also demonstrate its applicability for detecting simple hardware Trojans.Hence, DANA can be applied universally as the first step when investigating unknown netlists and provides major guidance for human analysts by structuring and condensing the otherwise incomprehensible sea of gates. Our implementation of DANA and all synthesized netlists are available as open source on GitHub.
    Type of Medium: Online Resource
    ISSN: 2569-2925
    Language: Unknown
    Publisher: Universitatsbibliothek der Ruhr-Universitat Bochum
    Publication Date: 2020
    detail.hit.zdb_id: 2921482-8
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  • 2
    Online Resource
    Online Resource
    Universitatsbibliothek der Ruhr-Universitat Bochum ; 2021
    In:  IACR Transactions on Cryptographic Hardware and Embedded Systems ( 2021-08-11), p. 412-446
    In: IACR Transactions on Cryptographic Hardware and Embedded Systems, Universitatsbibliothek der Ruhr-Universitat Bochum, ( 2021-08-11), p. 412-446
    Abstract: Over the last decade attacks have repetitively demonstrated that bitstream protection for SRAM-based FPGAs is a persistent problem without a satisfying solution in practice. Hence, real-world hardware designs are prone to intellectual property infringement and malicious manipulation as they are not adequately protected against reverse-engineering.In this work, we first review state-of-the-art solutions from industry and academia and demonstrate their ineffectiveness with respect to reverse-engineering and design manipulation. We then describe the design and implementation of novel hardware obfuscation primitives based on the intrinsic structure of FPGAs. Based on our primitives, we design and implement LifeLine, a hardware design protection mechanism for FPGAs using hardware/software co-obfuscated cryptography. We show that LifeLine offers effective protection for a real-world adversary model, requires minimal integration effort for hardware designers, and retrofits to already deployed (and so far vulnerable) systems.
    Type of Medium: Online Resource
    ISSN: 2569-2925
    Language: Unknown
    Publisher: Universitatsbibliothek der Ruhr-Universitat Bochum
    Publication Date: 2021
    detail.hit.zdb_id: 2921482-8
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  • 3
    Online Resource
    Online Resource
    Universitatsbibliothek der Ruhr-Universitat Bochum ; 2018
    In:  IACR Transactions on Cryptographic Hardware and Embedded Systems ( 2018-08-14), p. 293-330
    In: IACR Transactions on Cryptographic Hardware and Embedded Systems, Universitatsbibliothek der Ruhr-Universitat Bochum, ( 2018-08-14), p. 293-330
    Abstract: In today’s Integrated Circuit (IC) production chains, a designer’s valuable Intellectual Property (IP) is transparent to diverse stakeholders and thus inevitably prone to piracy. To protect against this threat, numerous defenses based on the obfuscation of a circuit’s control path, i.e. Finite State Machine (FSM), have been proposed and are commonly believed to be secure. However, the security of these sequential obfuscation schemes is doubtful since realistic capabilities of reverse engineering and subsequent manipulation are commonly neglected in the security analysis. The contribution of our work is threefold: First, we demonstrate how high-level control path information can be automatically extracted from third-party, gate-level netlists. To this end, we extend state-of-the-art reverse engineering algorithms to deal with Field Programmable Gate Array (FPGA) gate-level netlists equipped with FSM obfuscation. Second, on the basis of realistic reverse engineering capabilities we carefully review the security of state-of-the-art FSM obfuscation schemes. We reveal several generic strategies that bypass allegedly secure FSM obfuscation schemes and we practically demonstrate our attacks for a several of hardware designs, including cryptographic IP cores. Third, we present the design and implementation of Hardware Nanomites, a novel obfuscation scheme based on partial dynamic reconfiguration that generically mitigates existing algorithmic reverse engineering.
    Type of Medium: Online Resource
    ISSN: 2569-2925
    Language: Unknown
    Publisher: Universitatsbibliothek der Ruhr-Universitat Bochum
    Publication Date: 2018
    detail.hit.zdb_id: 2921482-8
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  • 4
    Online Resource
    Online Resource
    Springer Science and Business Media LLC ; 2021
    In:  Journal of Cryptographic Engineering Vol. 11, No. 3 ( 2021-09), p. 299-315
    In: Journal of Cryptographic Engineering, Springer Science and Business Media LLC, Vol. 11, No. 3 ( 2021-09), p. 299-315
    Type of Medium: Online Resource
    ISSN: 2190-8508 , 2190-8516
    Language: English
    Publisher: Springer Science and Business Media LLC
    Publication Date: 2021
    detail.hit.zdb_id: 2594302-9
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  • 5
    Online Resource
    Online Resource
    Institute of Electrical and Electronics Engineers (IEEE) ; 2021
    In:  IEEE Design & Test Vol. 38, No. 1 ( 2021-2), p. 14-21
    In: IEEE Design & Test, Institute of Electrical and Electronics Engineers (IEEE), Vol. 38, No. 1 ( 2021-2), p. 14-21
    Type of Medium: Online Resource
    ISSN: 2168-2356 , 2168-2364
    Language: Unknown
    Publisher: Institute of Electrical and Electronics Engineers (IEEE)
    Publication Date: 2021
    detail.hit.zdb_id: 2714080-5
    detail.hit.zdb_id: 2729075-X
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