In:
Applied Physics Letters, AIP Publishing, Vol. 107, No. 18 ( 2015-11-02)
Abstract:
A hybrid P/N channel junctionless (JL) thin-film transistor (TFT) with back-gate bias (Vbg) has been demonstrated. By applying negative bias of Vbg = −8 V in gate length of 50 nm shows excellent SS ( & lt;90 mV/dec), a negligible drain induced barrier lowering (DIBL), increased Ion versus decreased Ioff (ratio & gt; 108), and high Vth modulation. The increased Ion simultaneously decreased Ioff via negative Vbg is attributed to smaller surface E-field at ON-state, significantly reducing the impact on interface traps and thinner effective channel thickness at OFF-state, improving gate controllability. Hence, hybrid P/N JL-TFT with Vbg is a promising for low power circuit, power management, and System-on-Chip applications.
Type of Medium:
Online Resource
ISSN:
0003-6951
,
1077-3118
Language:
English
Publisher:
AIP Publishing
Publication Date:
2015
detail.hit.zdb_id:
211245-0
detail.hit.zdb_id:
1469436-0
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