In:
Japanese Journal of Applied Physics, IOP Publishing, Vol. 36, No. 7R ( 1997-07-01), p. 4289-
Abstract:
In this paper, the effects of large-tilted-angle p-pocket (LAP) implantation on the performance and reliability of stacked-gate memory cell are investigated. The utilization of LAP process achieves the improved programming efficiency and reduced punchthrough susceptibility. The 45° LAP cell featuring a fastest programming speed, however, would not be desirable due to the seriously aggravated read current degradation, drain/read disturbance, and early snap-back breakdown. The cells with 0° and 30° tilted angle are the feasible cells with the moderate programming performance and acceptable reliability constraints. Furthermore, the 0° LAP cell is preferred for the fact that it exhibits the desirable read current than that in 30° cell. Based on the cell performance and reliability consideration, the 0° p-pocket implanted cell is the optimal angle among 0°, 30° and 45° for the future scaling of stacked-gate memory cell.
Type of Medium:
Online Resource
ISSN:
0021-4922
,
1347-4065
DOI:
10.1143/JJAP.36.4289
Language:
Unknown
Publisher:
IOP Publishing
Publication Date:
1997
detail.hit.zdb_id:
218223-3
detail.hit.zdb_id:
797294-5
detail.hit.zdb_id:
2006801-3
detail.hit.zdb_id:
797295-7
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