In:
ACM SIGARCH Computer Architecture News, Association for Computing Machinery (ACM), Vol. 39, No. 3 ( 2011-06-22), p. 271-282
Abstract:
As microprocessor chips integrate a growing number of cores, the issue of interconnection becomes more important for overall system performance and efficiency. Compared to traditional distributed shared-memory architecture, chip-multiprocessors offer a different set of design constraints and opportunities. As a result, a conventional packet-relay multiprocessor interconnect architecture is a valid, but not necessarily optimal, design point. For example, the advantage of off-the-shelf interconnect and the in-field scalability of the interconnect are less important in a chip-multiprocessor. On the other hand, even with worsening wire delays,packet switching represents a non-trivial component of overall latency. In this paper, we show that with straight forward optimizations, the traffic between different cores can be kept relatively low. This in turn allows simple shared-medium interconnects to be built using communication circuits driving transmission lines. This architecture offers extremely low latencies and can support a large number of cores without the need for packet switching, eliminating costly routers.
Type of Medium:
Online Resource
ISSN:
0163-5964
DOI:
10.1145/2024723.2000097
Language:
English
Publisher:
Association for Computing Machinery (ACM)
Publication Date:
2011
detail.hit.zdb_id:
2088489-8
detail.hit.zdb_id:
186012-4
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