In:
ACM SIGARCH Computer Architecture News, Association for Computing Machinery (ACM), Vol. 11, No. 3 ( 1983-06-30), p. 151-157
Abstract:
This paper describes the architecture of a dynamically microprogrammable computer with low-level parallelism, called QA-2, which is designed as a high-performance, local host computer for laboratory use. The architectural principle of the QA-2 is the marriage of high-speed, parallel processing capability offered by four powerful Arithmetic and Logic Units (ALUs) with architectural flexibility provided by large scale, dynamic user-microprogramming. By changing its writable control storage dynamically, the QA-2 can be tailored to a wide spectrum of research-oriented applications covering high-level language processing and real-time processing. The QA-2 employs four identical ALUs which are independently controlled by the different fields of a 256-bit microinstruction. Sharing one uniform register file (6-kBytes), the ALUs can perform mutually independent/dependent operations on four sets of variable length operands (max. 4-Bytes × 4). In main memory accessing, four sets of variable length data (max. 4-Bytes × 4) can be simultaneously read from or written into different/continuous locations. In addition, structured microprogramming is possible because the QA-2 supports natural control structures such as an IF f(logic variables) THEN (CALL, GOTO or RETURN) ELSE (CALL,GOTO or RETURN) statement. All these features combine to yield an extensive microprogramming capability with which the user can tailor the QA-2 to his problems at hand.
Type of Medium:
Online Resource
ISSN:
0163-5964
DOI:
10.1145/1067651.801650
Language:
English
Publisher:
Association for Computing Machinery (ACM)
Publication Date:
1983
detail.hit.zdb_id:
2088489-8
detail.hit.zdb_id:
186012-4
Permalink
