In:
ACM SIGARCH Computer Architecture News, Association for Computing Machinery (ACM), Vol. 33, No. 3 ( 2005-06), p. 33-40
Abstract:
A SuperH™ embedded processor core SH-X implemented in a 130-nm CMOS process running at 400 MHz achieved 720 MIPS and 2.8 GFLOPS at a power of 250 mW under worst-case conditions. It has a dual-issue seven-stage pipeline architecture, but reaches the 1.8 MIPS/MHz of the previous five-stage processor. The on-chip memory configuration is tuned for digital consumer appliances. A new resume-standby mode enables a standby current of less than 100, μA and a 3-ms recovery time. The processor meets the requirements of a wide range of applications, and is suitable for digital appliances aimed at the consumer market, such as cellular phones, digital still/video cameras, and car navigation systems.
Type of Medium:
Online Resource
ISSN:
0163-5964
DOI:
10.1145/1101868.1101875
Language:
English
Publisher:
Association for Computing Machinery (ACM)
Publication Date:
2005
detail.hit.zdb_id:
2088489-8
detail.hit.zdb_id:
186012-4
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