Abstract: Ge is of great interest as a candidate channel material for future CMOS devices due to its high intrinsic carrier mobility. To translate this potential into CMOS, high-quality gate-stack and source/drain (S/D) junction formations are essential. We fabricated Ge n- and p-MOSFETs using the gate-stack formation by bilayer (SiO 2 /GeO 2 ) passivation and using S/D junction formations by thermal diffusion of P and ion implantation of B. The electron and hole channel mobilities of the fabricated MOSFETs were 1097 and 376 cm 2 V -1 s -1 , respectively, despite the very thin GeO 2 thickness. We will present the detailed fabrication method and device performance.

Abstract: Uniaxial strain was introduced to Si-on-insulator (SOI) substrate by SiN deposition using electron cyclotron resonance sputtering followed by gate-opening using lift-off technique. Then thermal treatments were performed at different temperatures. Strain-relaxation was observed by Raman spectroscopy. Photolumine-scence (PL) was used to evaluate defects generated during strain-relaxation. Defect-related PL signal was observed for the thermally-treated strained channel. The intensity of defect-related PL signal increased with increasing annealing temperature. The energy position and profile of defect-related PL signal also varied with annealing temperature and SiN thickness.

Abstract: We investigated the Al post metallization annealing (PMA) effect on Al 2 O 3 /GeO X /Ge gate stacks. The Al-PMA is effective for Al 2 O 3 /GeO X /Ge gate stacks, similar to the case of SiO 2 /GeO 2 gate stack. It was found that interface states density in the lower half of the band gap and slow trap density can be reduced by Al-PMA at 400°C. However, a serious problem occurred in the metal source/drain (S/D) MOSFET fabricated using the gate stack with Al-PMA, which was poor electrical isolation between gate and S/D. It was found that Al-PMA at 400°C caused the reaction of Al with Al 2 O 3 film on the S/D side wall, resulting in a decrease in insulating quality of Al 2 O 3 film. To solve this problem, we demonstrated a method for depositing a thin SiO 2 film on the S/D side wall.

Abstract: 1. Introduction Ge has been received much attention as the next generation semiconductor materials due to its attractive characteristics such as high carrier mobility[1] and narrow bandgap corresponding near infrared wavelength[2] . In order to utilize its characteristics for the applications, Ge-on-Insulator (GOI) structure is necessary. Several fabrication methods for GOI have been suggested such as wafer bonding and mechanical thinning[3], Smart-Cut TM [4,5], and SiGe condensation[6] . It is well known Smart-Cut TM is widely used for commercial Si-on-Insulator (SOI) fabrication. However, Ge is more sensitive to damages caused by ion implantation and difficult to recover damages completely. Therefore, the best way for GOI fabrication have not been developed. In early stage of SOI R & D, many approaches were proposed, too[7]. Wafer bonding and etchback is one of the simplest technique, and the advantage of this method is any damages due to ion implantation or mechanical stress are not induced to the top semiconductor layer. Therefore, we focused on etchback technique for GOI fabrication. It is necessary to develop appropriate Ge etching method with moderate etching rate and keeping or improving surface flatness. In this study, we aim to develop appropriate etching method of Ge for etchback GOI fabrication. 2. Experimental and results We used single side mirror polished Ge wafer with a thickness of 500 μm. Figure 1 shows the experimental procedure in this study. The original polished top surface was covered by photoresist to avoid etching from this side. Firstly, we confirmed HF + HNO 3 mixture solution for Ge etching because it is widely known as etching solution for Si. Figure 2 shows optical microscope images for the back side (non-polished side) of (100)-oriented Ge wafer (a) before etching and (b) after etching by HF + HNO 3 for 7 minutes. By etching, surface uniformity drastically improved. So, wet etching can be used for Ge thinning and planarization. However, this solution reacts handle Si substrate of GOI, too. As an alternative etching solution, we selected HF + H 2 O 2 mixture[8]. Figure 3 shows the etching result of (100)-oriented Ge etched by HF + H 2 O 2 + H 2 O (7:7:6) solution. Although Ge was etched similar to Fig. 2(b), surface uniformity was inferior to HF + HNO 3 etching. To improve surface uniformity, CH 3 COOH was added as diluent instead of H 2 O because politic amount of CH 3 COOH into HF + HNO 3 solution leads isotropic etching and mirror plane on Si surface[9]. Figures 4 shows the etching results of (100)-oriented Ge by HF + H 2 O 2 + CH 3 COOH (1:1:1) solution. Surface uniformity improved than Fig. 3 and there is no orientation dependence (data not shown). Therefore, isotropic etching occurs on Ge surface. The average etching rate in the first 20 minutes calculated from the lost masses was 7.9 μm/min. It should be noted any agitation was not carried out during etching and longer etching time leads decreasing of etching rate. Possible etching reaction is expressed as[10]: 2CH 3 COOH + 2H 2 O 2 → 2CH 3 COOOH + 2H 2 O (1) Ge + 2CH 3 COOOH + 2 e - → Ge 2+ + 2CH 3 COO - + 2OH - (2) As further investigation of surface uniformity, atomic force microscope (AFM) observation was carried out. Figure 5 shows AFM images for backside of (100)-oriented Ge etched for 110 minutes. The RMS of 30×30 μm 2 area is 0.48 nm. Compared with the RMS of original backside ( 〉 5 μm), the surface flatness is improved drastically. In the conference, electrical characteristics of etched surface will be presented. 3. Conclusions For etchback GOI fabrication, we study isotropic etching for Ge. HF + H 2 O 2 + CH 3 COOH mixture solution can etch Ge isotropic and improving surface uniformity. This solution has a potential as etching solution for etchback to make GOI structure. Acknowledgements This work was supported by JSPS KAKENHI Grant Numbers 19K15028 and 19H05616. Appendix Original concentrations of the chemicals in this study are HF: 49 wt%, HNO 3 : 69 wt%, H 2 O 2 : 30 wt%, and CH 3 COOH: 99.7 wt%. All compounding ratios in this article are volume rate. References [1] A. Toriumi et al ., JJAP, 57 , 010101 (2018). [2] G. Z. Mashanovich et al ., Opt. Mat. Express, 8 , 2276 (2018). [3] Z. Zheng et al ., APL, 109 , 023503 (2016). [4] J. Kang et al ., Mat. Sci. Semicond. Process., 42 , 259 (2016). [5] K. Yamamoto et al ., ECS trans. 93 , 73 (2019). [6] K.-W. Jo et al ., APL, 114 , 062101 (2019). [7] W. P. Maszara, JES, 138 , 341 (1991). [8] B. Schwartz, JES, 114 , 285 (1967). [9] S. Wolf et al., Silicon Processing for the VLSI Era Volume 1, Lattice Press. (1990). [10] T. K. Carns et al., JES, 142 , 1260 (1995). Figure 1

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Abstract: Electroorganic synthesis is an attractive method, in which only electrons serve as reagent and therefore complies with a “green chemistry” condition. In addition, reactions of electroorganic synthesis can be regarded as a special heterogeneous catalytic one. Furthermore, products can be obtained with high selectivity and efficiency by optimizing a reaction condition, such as electrode materials, potential, and others. Recently, a boron-doped diamond (BDD) electrode attracts much attention in the field of electroorganic chemistry. This is particularly because the BDD electrode enables to generate active species such as a hydroxyl radical with high efficiency under an appropriate electrolysis condition. Here, we report on the electroorganic synthesis using BDD electrode, especially TEMPO-mediated oxidation of the 1,2-diol derivative. TEMPO (2,2,6,6,-tetramethylpyperidine-1-oxyl) has been widely used as a catalyst in organic synthesis, for converting primary alcohol to an aldehyde selectively even in the presence of a secondary alcohol. However, the conventional TEMPO oxidation reaction requires a co-oxidant such as sodium hypochlorite and a hypervalent iodine compound. First, we prepared an electrolyte solution of TEMPO (0.1 mmol) and LiClO 4 (0.1 M in CH 3 CN) or n -Bu 4 N•PF 6 (0.1 M in CH 2 Cl 2 ). Cyclic voltammetry (CV) was performed to examine an electrochemical behavior of TEMPO. For CV measurementsusinan undivided cell, BDD, Pt wire, and Ag/AgCl electrodes were used as the working, counter, and reference electrode, respectively. Next, for an electrolysis experiment, a diol substrate, 3-phenyl-1,2-propanediol, was synthesized according to the previous report. The diol substrate (10 mmol) was added to the electrolyte solution (10 mL), and a constant current electrolysis (1 F/mol for the diol substrate) was conducted at room temperature. After electrolysis, a resulting compound containing in solution was evaluated by 1 H NMR. For acetylation of a hydroxyl group in oxidized products, pyridine (20 mmol) and acetic anhydride (20 mmol) was added and stirred at room temperature for 6 h. The resulting acetylated products were analyzed by a thin layer chromatography (TLC). In the cyclic voltammogram of TEMPO solution, oxidation and reduction peaks of TEMPO were clearly observed at 0.8 V and 0.6 V ( vs. Ag/AgCl), respectively. On the other hand, the reduction peak of TEMPO almost disappeared in the presence of 3-phenyl-1,2-propanediol. Based on the reaction mechanism of TEMPO oxidation, such a CV behavior would ascribed to oxidation of 3-phenyl-1,2-propanediol substrate by TEMPO catalyst. Next, we examined the solvent dependence of TEMPO-mediated electro-oxidation. When using CH 3 CN electrolyte solution, surface of the Pt cathode was covered with a black film and the current dropped immediately. On the other hand, in case of CH 2 Cl 2 electrolyte solution, a couple of oxidized products were detected by a TLC analysis. Furthermore, in the 1 H NMR spectrum, a signal at 10 ppm derived from an aldehyde group was detected. We investigated TEMPO-mediated selective electro-oxidation using a BDD electrode. First, we confirmed both oxidation and reduction of TEMPO on a BDD electrode. Next, TEMPO-mediated electro-oxidation of 3-phenyl-1,2-propanediol gave a couple of products containing an aldehyde group.

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Abstract: 1) Introduction To fabricate high-performance Ge MOSFETs, a high-quality gate-stack of Ge is essential. Although a GeO 2 interlayer is very effective to improve the interface quality between Ge and gate-stack, the existence of large number of border-traps (BTs) in GeO 2 is still a serious issue that degrades the performance of Ge MOSFETs. Therefore, the BT characterization for GeO 2 /Ge structure is desired. In this work, we intentionally used relatively strong injection to carry out deep-level transient spectroscopy (DLTS) measurements. By separating out interface traps (IT) contribution from DLTS signals, we extracted the BT signals and calculated BT concentrations ( N bt ). BTs also exist in the SiO 2 /Si structure, and DLTS has been applied to evaluate N bt for Si MOSCAPs [1]. However, owing to the relatively low N bt in SiO 2 and the large band-offsets at the SiO 2 /Si interface, BTs do not cause serious problems in Si MOSFETs. Therefore, an N bt evaluation has not been studied intensely. As for the GeO 2 /Ge structure, the BT problem becomes serious because the N bt in GeO 2 is relatively high and the band offsets at the GeO 2 /Ge interface are lower than those of SiO 2 /Si. Actually, when we measured the IT density ( D it ) for a GeO 2 /Ge structure, we found that the DLTS signal intensity clearly increased with increasing intensity of the injection pulse [2], which must have resulted from the BTs in GeO 2 . We believe that DLTS is a promising method to evaluate BTs for Ge MOSCAPs. In this presentation, BT evaluation using the DLTS method for Ge MOSCAP is introduced. Both D it and N bt are evaluated for Ge MOSCAPs fabricated by post-passivation thermal oxidation (PTO) and electron cyclotron resonance (ECR) plasma oxidation. In addition, the effects of Al post metallization annealing (Al-PMA) are also investigated. 2) Experimental Both p- and n-type (100) Ge substrates with respective doping concentrations of 2.3x10 16 and 9.3x10 15 cm -3 were used. After substrate cleaning, SiO 2 /GeO 2 bilayer passivation was performed [3]. Here, the thicknesses of SiO 2 and GeO 2 layers were ~1 nm each. Next, PTO was performed at 550°C for 15 min or 425°C for 9 h in O 2 ambient. After 14-nm-thick SiO 2 was deposited on the both samples, the annealing at 400°C for 30 min in N 2 was performed. Then, the Al gate film was deposited on the SiO 2 surface by thermal evaporation. Before the electrode patterning, an optional PMA was carried out at 300°C for 30 min in N 2 , which is the Al-PMA. The EOTs of the MOSCAPs with PTO at 550 and 425°C were 19.5 and 16.8 nm, corresponding to GeO 2 thicknesses of 6.0 and 3.3 nm, respectively. DLTS measurements were performed using a lock-in integrator. The MOSCAP was reverse-biased at V R and was applied the pulse bias of V P from V R . V AP (=| V P - V FB |, V FB : flat band voltage) is the accumulation pulse voltage, which is an important parameter for the BT analysis, because the injection pulse intensity ( E AP ) at the GeO 2 /Ge interface is given by E AP = V AP /EOT. Frequency ( f ) and pulse width ( t w ) are also important parameters for selecting the observed BT position ( z 0 ) and for filling with carriers into BTs, respectively. 3) Summary of the r esults By using p-type MOSCAPs, BTs at the position of 0.4 nm from the GeO 2 /Ge interface were measured. The energy of these BTs was centralized at the position near to the valence band edge of Ge, and their N bt was in the range of 10 17 –10 18 cm -3 . By using n-type MOSCAPs, BTs at the position range of 2.8–3.4 nm from the GeO 2 /Ge interface were measured, of which N bt varied little in the depth direction. The energy of these BTs was distributed in a relatively wide range near to the conduction band edge of Ge, and their N bt was approximately one order of magnitude higher than those measured by p-MOSCAPs. This high N bt value might originate from the states of the valence alternation pair with energy close to 1 eV above the conduction band edge of Ge. We also found that Al-PMA can passivate both ITs and BTs near to the valence band edge of Ge but not those near to the conduction band edge. Acknowledgement This work was supported by (JSPS) KAKENHI (grant No. 17H03237). References [1] H. Lakhdari, D. Vuillaume, and J. C. Bourgoin, Phys. Rev. B 38 , 13124 (1988). [2] D. Wang, S. Kojima, K. Sakamoto, K. Yamamoto, and H. Nakashima, J. Appl. Phys. 112 , 083707 (2012). [3] K. Hirayama, R. Ueno, Y. Iwamura, K. Yoshino, D. Wang, H. Yang, H. Nakashima, Jpn. J. Appl. Phys., 50, 04DA10-1-5 (2011).