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  • The Electrochemical Society  (11)
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  • The Electrochemical Society  (11)
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  • 1
    Online Resource
    Online Resource
    Investigation of SiGeB Epitaxy on Different Film Substrates
    The Electrochemical Society ; 2014
    In:  ECS Transactions Vol. 60, No. 1 ( 2014-02-27), p. 133-137
    Details
    In: ECS Transactions, The Electrochemical Society, Vol. 60, No. 1 ( 2014-02-27), p. 133-137
    Abstract: Selective epitaxial embedded SiGe(B) (e-SiGe) is widely used for Source/Drain in advanced CMOS technologies for introducing compressive strain to the PMOS channel which improves the hole mobility. In this paper, we investigated SiGeB epitaxy on different substrates including SiGe, Si:B, SiGeB and also dielectric films including ALD/ CVD SiN, thermal/CVD SiO2. For SiGeB epitaxy on crystallized film substrates, results show that Germanium would prevent Boron inter-diffusion between the substrate and the following deposited SiGeB. Growth Rate (GR) of the epitaxy e-SiGe film is also investigated. A combination of the SiGeB film concentration and GR study shows that Boron concentration and strain introduced by lattice mismatch between the substrate and the epitaxial film are two competitive factors to the GR. The film grows faster when Boron concentration is higher while larger strain would degrade the GR. Selectivity study shows that CVD SiN film have the best selectivity. We also investigated the film selectivity before and after thermal anneal. Results show that film selectivity become worse after thermal anneal.
    Type of Medium: Online Resource
    ISSN: 1938-5862 , 1938-6737
    URL: Article
    DOI: 10.1149/06001.0133ecst
    Language: Unknown
    Publisher: The Electrochemical Society
    Publication Date: 2014
    detail.hit.zdb_id: 2217591-X
    detail.hit.zdb_id: 2251888-5
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  • 2
    Online Resource
    Online Resource
    Investigation of Poly Film Application in Advanced MOSFET Technology
    The Electrochemical Society ; 2014
    In:  ECS Transactions Vol. 60, No. 1 ( 2014-02-27), p. 507-511
    Details
    In: ECS Transactions, The Electrochemical Society, Vol. 60, No. 1 ( 2014-02-27), p. 507-511
    Abstract: Un-doped poly process becomes more critical with CMOS scaling down as gate electrode in advanced Poly/SiON process and dummy poly in HK/MG technology. The poly grain size and roughness impact the device mis-match between different transistors like NMOS off current fluctuation and it plays as dummy poly role in HK/MG technology. It is necessary to investigate the poly grain size after deposition and thermal process as it will change the poly grain structure. In this paper, top view Scanning Electrical Microscope (SEM), X-ray Diffraction (XRD),Atomic Force Microscopy (AFM) and Transmission Electron Microscope (TEM) are used to characterize the poly grain size, crystalline fraction, surface roughness and poly structure. It is find that the poly grain becomes larger after thermal, especially spike anneal. A smaller grain size of undoped poly with lower roughness was achieved by process tuning of temperature, pressure, gas flow etc which was implemented in device wafer and get improved performance.
    Type of Medium: Online Resource
    ISSN: 1938-5862 , 1938-6737
    URL: Article
    DOI: 10.1149/06001.0507ecst
    Language: Unknown
    Publisher: The Electrochemical Society
    Publication Date: 2014
    detail.hit.zdb_id: 2217591-X
    detail.hit.zdb_id: 2251888-5
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  • 3
    Online Resource
    Online Resource
    Investigation of a Promising Chemical for BEOL Ultra Low K Cleaning of 28nm Node and Beyond
    The Electrochemical Society ; 2014
    In:  ECS Transactions Vol. 60, No. 1 ( 2014-02-27), p. 379-382
    Details
    In: ECS Transactions, The Electrochemical Society, Vol. 60, No. 1 ( 2014-02-27), p. 379-382
    Abstract: In this paper, novel cleaning chemical for BEOL dual damascene cleaning was evaluated. The cleaning performance mainly focus on electrical property of Cu interconnect and physical impact on dual damascene structure such as Cu erosion and TiN pullback profile. It’s found Cu erosion is well controlled by Cu inhibitor in the chemical, while TiN pullback amount can be controlled by H 2 O 2 ratio, process time. The DIW rinse hard removability of the Cu-inhibitor and its impact on device reliability also discussed in this paper. This drawback can be fixed by low temperature anneal to decompose the Cu and inhibitor complex.
    Type of Medium: Online Resource
    ISSN: 1938-5862 , 1938-6737
    URL: Article
    DOI: 10.1149/06001.0379ecst
    Language: Unknown
    Publisher: The Electrochemical Society
    Publication Date: 2014
    detail.hit.zdb_id: 2217591-X
    detail.hit.zdb_id: 2251888-5
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  • 4
    Online Resource
    Online Resource
    Ultrathin Interfacial Layer (UTIL) Formation and Its Application in HKMG for Advance CMOS Technology
    The Electrochemical Society ; 2014
    In:  ECS Transactions Vol. 60, No. 1 ( 2014-02-27), p. 681-685
    Details
    In: ECS Transactions, The Electrochemical Society, Vol. 60, No. 1 ( 2014-02-27), p. 681-685
    Abstract: This paper investigates two kinds of ultra thin interfacial layer (UTIL) include SiO 2 and SiON, their formation and application in HKMG for advanced CMOS technology. Compare to SiO 2 UTIL, SiON UTIL demonstrates good NMOS EOT uniformity, low gate leakage current, but high defect density. Beside offline characterization, these two kinds of interfacial layer were also investigated their application in semiconductor device wafer for electronic test. It is found that the ultrathin SiON as interfacial layer exhibits a lower Tinv and better leakage performance under same physical thickness as compared to SiO 2 . However, PMOS device mobility suffers some degradation, which is contributed to N diffusion into the interface between UTIL and substrate, as verified by N SIMS profile. Different N atom concentration and thickness of UTIL SiON and their impact on device performance were also discussed in this paper. In general, UTIL SiON film is a promising candidate interfacial layer for HKMG advanced CMOS technology to meet EOT scaling requirement.
    Type of Medium: Online Resource
    ISSN: 1938-5862 , 1938-6737
    URL: Article
    DOI: 10.1149/06001.0681ecst
    Language: Unknown
    Publisher: The Electrochemical Society
    Publication Date: 2014
    detail.hit.zdb_id: 2217591-X
    detail.hit.zdb_id: 2251888-5
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  • 5
    Online Resource
    Online Resource
    SiON Gate Dielectric Optimization for NBTI Improvement
    The Electrochemical Society ; 2011
    In:  ECS Transactions Vol. 34, No. 1 ( 2011-03-21), p. 719-724
    Details
    In: ECS Transactions, The Electrochemical Society, Vol. 34, No. 1 ( 2011-03-21), p. 719-724
    Abstract: Plasma nitride SiON films have been widely used as gate dielectric in advanced CMOS device fabrication since 90nm technology node. As a replacement material for conventional silicon dioxide, it can provide increased dielectric constant and serve as an effective boron barrier. Post nitridation anneal (PNA), a critical step for plasma nitride SiON formation, is used to stabilize plasma incorporated nitrogen radicals and ions through form thermal stable Si-N banding. Furthermore, PNA can repair the damaged Si/SiO2 interface by interface substrate re-oxidation under oxygen contained ambient. In this work, several PNA conditions were studied. Their effect on transistor performance and PMOS NBTI (Negative Bias Temperature Instability) lifetime were evaluated. It demonstrates that NBTI performance can be improved 20% by PNA process optimizing, while keeping the same Tinv thickness and Ioff/Ion performance.
    Type of Medium: Online Resource
    ISSN: 1938-5862 , 1938-6737
    URL: Article
    DOI: 10.1149/1.3567663
    Language: Unknown
    Publisher: The Electrochemical Society
    Publication Date: 2011
    detail.hit.zdb_id: 2217591-X
    detail.hit.zdb_id: 2251888-5
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  • 6
    Online Resource
    Online Resource
    A Comprehensive Study of SiGe Source/ Drain Local Stress by Nano Beam Diffraction
    The Electrochemical Society ; 2013
    In:  ECS Transactions Vol. 52, No. 1 ( 2013-03-08), p. 33-37
    Details
    In: ECS Transactions, The Electrochemical Society, Vol. 52, No. 1 ( 2013-03-08), p. 33-37
    Abstract: Compressive stress introduced by source/drain (S/D) SiGe is widely used in 45nm node and beyond advanced technology which boost the P-channel hole mobility. Quantitive measurement of localized stress in channel is limited by the scaling shrinking. Transmitted electron microscopy- Nano Beam Diffraction (TEM-NBD) is an effective method for the local stress distribution measurement in channel and well area derived from S/D Si 1-x Ge x . In this paper, we study the channel strain from the following aspect, including i) active area (AA) width, ii) S/D recess shape, iii) S/D recess trench depth, and iv) Germanium (Ge), Boron (B) concentration of S/D Si 1-x Ge x and Ge, B distribution profile. It is revealed that strain has strong relation with these factors. Pitch with narrow AA width shows lower strain than that of wider AA width. S/D recess shape affects the proximity which is critical for the stress derived from S/D SiGe transmit to channel location. Moreover, S/D recess trench depth determines the volume of filled SiGe then affect the strain to channel. Both of the Ge, B concentration of S/D SiGe and the distribution profile directly affects the lattice mismatch which results in the strain. In general, all these factors affect the volume of the filled SiGe and Ge concentration which eventually determine the strain of S/D to channel area.
    Type of Medium: Online Resource
    ISSN: 1938-5862 , 1938-6737
    URL: Article
    DOI: 10.1149/05201.0033ecst
    Language: Unknown
    Publisher: The Electrochemical Society
    Publication Date: 2013
    detail.hit.zdb_id: 2217591-X
    detail.hit.zdb_id: 2251888-5
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  • 7
    Online Resource
    Online Resource
    Influence of Oxide Interlayer by TiN Metal Gate in High-k First CMOS Devices
    The Electrochemical Society ; 2017
    In:  ECS Journal of Solid State Science and Technology Vol. 6, No. 5 ( 2017), p. P296-P299
    Details
    In: ECS Journal of Solid State Science and Technology, The Electrochemical Society, Vol. 6, No. 5 ( 2017), p. P296-P299
    Type of Medium: Online Resource
    ISSN: 2162-8769 , 2162-8777
    URL: Article
    DOI: 10.1149/2.0221705jss
    Language: English
    Publisher: The Electrochemical Society
    Publication Date: 2017
    detail.hit.zdb_id: 2674149-0
    detail.hit.zdb_id: 2680340-9
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  • 8
    Online Resource
    Online Resource
    Effect of the Interfacial SiO2 Layer on High-k Gate Stacks
    The Electrochemical Society ; 2013
    In:  ECS Transactions Vol. 52, No. 1 ( 2013-03-08), p. 657-663
    Details
    In: ECS Transactions, The Electrochemical Society, Vol. 52, No. 1 ( 2013-03-08), p. 657-663
    Abstract: Interfacial oxide (IL) /high-k (HK) gate dielectric stack is widely used in 45nm logic technology and beyond nodes. Interfacial oxide, which is buffer layer between silicon substrate and HK dielectric, is a crucial factor to control Silicon/IL, IL/high-k interface charge and high-k film quality. In this work, atom layer deposition (ALD) Hf based HK film is deposited on two classes of IL by thermal oxidation (process A or B) and chemical oxidation (process C or D), respectively. XPS is used to characterize the film bonding energy, while non contact CV and spectroscopic ellipsometry (SE) are used to characterize the interface trap. The electric properties of the film stacks are characterized by C-V and I-V curves. The results reveal that interface trap of chemical oxide film has positive surface voltage and less dense SiOx, as compared with that of thermal oxide. With the same interfacial oxide thickness and HK deposition process, the chemical oxide/HK stack got 3.4A thick EOT, which is about two orders lower leakage than that of thermal oxide/HfO 2 . It can be explained by the fact that chemical oxide had plenty of O-H bonds, which is good for ALD Hf based HK film nucleation and growth and resulted in good film quality. However, due to the high Si/chemical oxide interfacial charge, the chemical oxide/HfO 2 dielectric stack has a disadvantage of the larger C-V hysteresis.
    Type of Medium: Online Resource
    ISSN: 1938-5862 , 1938-6737
    URL: Article
    DOI: 10.1149/05201.0657ecst
    Language: Unknown
    Publisher: The Electrochemical Society
    Publication Date: 2013
    detail.hit.zdb_id: 2217591-X
    detail.hit.zdb_id: 2251888-5
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  • 9
    Online Resource
    Online Resource
    eSiGe Global and Micro Loading Effect Study in High Performance 45nm CMOS Technology
    The Electrochemical Society ; 2011
    In:  ECS Transactions Vol. 34, No. 1 ( 2011-03-21), p. 731-736
    Details
    In: ECS Transactions, The Electrochemical Society, Vol. 34, No. 1 ( 2011-03-21), p. 731-736
    Abstract: The embedded silicon germanium (eSiGe) is widely applied in advanced CMOS device fabrication to boost PMOS channel mobility. Beside selectivity, defect control and thermal compatibility, one big challenge of epitaxy growth SiGe process is loading effect between different product and different features. In this work, two precursors of SiH4 and SiH2Cl2 (DCS) were applied for SiGe epitaxy growth respectively. Their impact on embedded silicon germanium global and micro loading was investigated also. The results reveal some solutions to minimize the loading effect such as proper precursor selection, partial pressure optimization and silicon open space constraint.
    Type of Medium: Online Resource
    ISSN: 1938-5862 , 1938-6737
    URL: Article
    DOI: 10.1149/1.3567665
    Language: Unknown
    Publisher: The Electrochemical Society
    Publication Date: 2011
    detail.hit.zdb_id: 2217591-X
    detail.hit.zdb_id: 2251888-5
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  • 10
    Online Resource
    Online Resource
    Investigation of Laser Spike Anneal Dwell Time and It's Compatibility with Embedded-SiGe
    The Electrochemical Society ; 2011
    In:  ECS Transactions Vol. 34, No. 1 ( 2011-03-21), p. 737-742
    Details
    In: ECS Transactions, The Electrochemical Society, Vol. 34, No. 1 ( 2011-03-21), p. 737-742
    Abstract: Laser spike anneal (LSA) is applied in advanced CMOS device fabrication to achieve efficient dopant activation without excess dopant diffusion. Dwell time, defined as the ratio of full width at half maximum of laser beam and beam scan speed, is found to be a critical and effective knob in LSA processes. In this work, different dwell time of LSA and its impact on dope activation, junction profile, and compatibility with embedded SiGe (e-SiGe) was studied. Dwell time in the range of 800us to 275us has been investigated. LSA processes with different dwell time result in similar dopant activation and almost identical doping profile. On the other hand, reduced dwell time resulted in significant improvement in wafer warpage and overlay performance, when LSA is applied on CMOS devices with e-SiGe S/D pMOSFET. With electrical results consistent with offline characterization, this work indicated that lower dwell time LSA is more flexible and compatible with e-SiGe process for advanced CMOS devices.
    Type of Medium: Online Resource
    ISSN: 1938-5862 , 1938-6737
    URL: Article
    DOI: 10.1149/1.3567666
    Language: Unknown
    Publisher: The Electrochemical Society
    Publication Date: 2011
    detail.hit.zdb_id: 2217591-X
    detail.hit.zdb_id: 2251888-5
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