In:
Japanese Journal of Applied Physics, IOP Publishing, Vol. 55, No. 6 ( 2016-06-01), p. 063001-
Abstract:
A possible low-temperature fabrication process of a gate-stack for Ge-based spin metal–oxide–semiconductor field-effect transistor (MOSFET) is investigated. First, since we use epitaxial ferromagnetic Heusler alloys on top of the phosphorous doped Ge epilayer as spin injector and detector, we need a dry etching process to form Heusler-alloy/n + -Ge Schottky-tunnel contacts. Next, to remove the Ge epilayers damaged by the dry etching process, the fabricated structures are dipped in a 0.03% diluted H 2 O 2 solution. Finally, Al/SiO 2 /GeO 2 /Ge gate-stack structures are fabricated at 300 °C as a top gate-stack structure. As a result, the currents in the Ge-MOSFET fabricated here can be modulated by applying gate voltages even by using the low-temperature formed gate-stack structures. This low-temperature fabrication process can be utilized for operating Ge spin MOSFETs with a top gate electrode.
Type of Medium:
Online Resource
ISSN:
0021-4922
,
1347-4065
DOI:
10.7567/JJAP.55.063001
Language:
Unknown
Publisher:
IOP Publishing
Publication Date:
2016
detail.hit.zdb_id:
218223-3
detail.hit.zdb_id:
797294-5
detail.hit.zdb_id:
2006801-3
detail.hit.zdb_id:
797295-7
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