In:
Japanese Journal of Applied Physics, IOP Publishing, Vol. 51, No. 4S ( 2012-04-01), p. 04DC04-
Abstract:
An advanced method of the novel silicon-on-insulator (SOI) realization technology is proposed for the fabrication of SOI tri-gate transistors. Using the new method, 10 nm width SOI tri-gate transistors are successfully fabricated on standard Si bulk wafers, and result in excellent electrical characteristics after optimizing the processing parameters. Among others, low-cost and high manufacturability to fabricate SOI tri-gate transistors are advantages of the proposed method. Formed on the standard Si bulk wafer process, the SOI tri-gate transistors with gate length ( L G ) of 45 nm have reasonable threshold voltage ( V TH ) of 0.18 V and showed the enhanced current drivability up to 20%. They also demonstrated good short channel effect immunities: sub-threshold swing (SS) and drain induced barrier lowering (DIBL) were 70 mV/dec and 24 mV/V, respectively. Therefore, the novel method for the novel SOI realization technology proposed in this work will be one of the candidates for the scaling-down strategy in the future.
Type of Medium:
Online Resource
ISSN:
0021-4922
,
1347-4065
DOI:
10.1143/JJAP.51.04DC04
Language:
Unknown
Publisher:
IOP Publishing
Publication Date:
2012
detail.hit.zdb_id:
218223-3
detail.hit.zdb_id:
797294-5
detail.hit.zdb_id:
2006801-3
detail.hit.zdb_id:
797295-7
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