In:
Japanese Journal of Applied Physics, IOP Publishing, Vol. 19, No. S1 ( 1980-01-01), p. 187-
Abstract:
A speech synthesizer for PARCOR CODEC, using 2 µm E/D n-MOS microfabrication technology, is developed. The synthesis operation is executed through a multistage lattice filter which is organized by RAM, adder/substracter, and multiplier. The number of the filter stage can be altered to either 8 or 10 by an external signal, according to the demanded quality. The synthesis operation is fully controlled by the program stored in the ROM. Input signals of the synthesizer are the sound source parameter and PARCOR coefficients, and have a fixed point 2's complement format. Internal data bit length is 16 bits. The parallel multiplier used in the synthesizer achieves high speed operation and integration density using modified Booth's algorithm and cellular array formation. The measured maximum clock frequency and power dissipation of the synthesizer are 5 MHz and 450 mW, respectively.
Type of Medium:
Online Resource
ISSN:
0021-4922
,
1347-4065
DOI:
10.7567/JJAPS.19S1.187
Language:
Unknown
Publisher:
IOP Publishing
Publication Date:
1980
detail.hit.zdb_id:
218223-3
detail.hit.zdb_id:
797294-5
detail.hit.zdb_id:
2006801-3
detail.hit.zdb_id:
797295-7
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