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  • Association for Computing Machinery (ACM)  (3)
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  • Association for Computing Machinery (ACM)  (3)
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  • 1
    Online Resource
    Online Resource
    Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis
    Association for Computing Machinery (ACM) ; 2010
    In:  ACM Transactions on Design Automation of Electronic Systems Vol. 16, No. 1 ( 2010-11), p. 1-29
    Details
    In: ACM Transactions on Design Automation of Electronic Systems, Association for Computing Machinery (ACM), Vol. 16, No. 1 ( 2010-11), p. 1-29
    Abstract: Many techniques for power reduction in advanced RTL synthesis tools rely explicitly or implicitly on observability don’t-care conditions. In this article we propose a systematic approach to maximize the effectiveness of these techniques by generating power-friendly RTL descriptions in behavioral synthesis. This is done using operation gating , that is, explicitly adding a predicate to an operation based on its observability condition, so that the operation, once identified as unobservable at runtime, can be avoided using RTL power optimization techniques such as clock gating. We first introduce the concept of behavior-level observability and its approximations in the context of behavioral synthesis. We then propose an efficient procedure to compute an approximated behavior-level observability of every operation in a dataflow graph. Unlike previous techniques which work at the bit level in Boolean networks, our method is able to perform analysis at the word level, and thus avoids most computation effort with a reasonable approximation. Our algorithm exploits the observability-masking nature of some Boolean operations, as well as the select operation, and allows certain forms of other knowledge to be considered for stronger observability conditions. The approximation is proved exact for (acyclic) dataflow graphs when non-Boolean operations other than select are treated as black boxes. The behavior-level observability condition obtained by our analysis can be used to guide the operation scheduler to optimize the efficiency of operation gating. In a set of experiments on real-world designs, our method achieves an average of 33.9% reduction in total power; it outperforms a previous method by 17.1% on average and gives close-to-optimal solutions on several designs. To the best of our knowledge, this is the first time behavior-level observability analysis and optimization are performed during behavioral synthesis in a systematic manner. We believe that our idea can be applied to compiler transformations in general.
    Type of Medium: Online Resource
    ISSN: 1084-4309 , 1557-7309
    URL: Article
    DOI: 10.1145/1870109.1870113
    Language: English
    Publisher: Association for Computing Machinery (ACM)
    Publication Date: 2010
    detail.hit.zdb_id: 1501152-5
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    Online Resource
  • 2
    Online Resource
    Online Resource
    FPGA HLS Today: Successes, Challenges, and Opportunities
    Association for Computing Machinery (ACM) ; 2022
    In:  ACM Transactions on Reconfigurable Technology and Systems Vol. 15, No. 4 ( 2022-12-31), p. 1-42
    Details
    In: ACM Transactions on Reconfigurable Technology and Systems, Association for Computing Machinery (ACM), Vol. 15, No. 4 ( 2022-12-31), p. 1-42
    Abstract: The year 2011 marked an important transition for FPGA high-level synthesis (HLS), as it went from prototyping to deployment. A decade later, in this article, we assess the progress of the deployment of HLS technology and highlight the successes in several application domains, including deep learning, video transcoding, graph processing, and genome sequencing. We also discuss the challenges faced by today’s HLS technology and the opportunities for further research and development, especially in the areas of achieving high clock frequency, coping with complex pragmas and system integration, legacy code transformation, building on open source HLS infrastructures, supporting domain-specific languages, and standardization. It is our hope that this article will inspire more research on FPGA HLS and bring it to a new height.
    Type of Medium: Online Resource
    ISSN: 1936-7406 , 1936-7414
    URL: Article
    DOI: 10.1145/3530775
    Language: English
    Publisher: Association for Computing Machinery (ACM)
    Publication Date: 2022
    detail.hit.zdb_id: 2418475-5
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  • 3
    Online Resource
    Online Resource
    PIMap : A Flexible Framework for Improving LUT-Based Technology Mapping via Parallelized Iterative Optimization
    Association for Computing Machinery (ACM) ; 2018
    In:  ACM Transactions on Reconfigurable Technology and Systems Vol. 11, No. 4 ( 2018-12-31), p. 1-23
    Details
    In: ACM Transactions on Reconfigurable Technology and Systems, Association for Computing Machinery (ACM), Vol. 11, No. 4 ( 2018-12-31), p. 1-23
    Abstract: Modern FPGA synthesis tools typically apply a predetermined sequence of logic optimizations on the input logic network before carrying out technology mapping. While the “known recipes” of logic transformations often lead to improved mapping results, there remains a nontrivial gap between the quality metrics driving the pre-mapping logic optimizations and those targeted by the actual technology mapping. Needless to mention, such miscorrelations would eventually result in suboptimal quality of results. In this article, we propose PIMap, which couples logic transformations and technology mapping under an iterative improvement framework for LUT-based FPGAs. In each iteration, PIMap randomly proposes a transformation on the given logic network from an ensemble of candidate optimizations; it then invokes technology mapping and makes use of the mapping result to determine the likelihood of accepting the proposed transformation. By adjusting the optimization objective and incorporating required time constraints during the iterative process, PIMap can flexibly optimize for different objectives including area minimization, delay optimization, and delay-constrained area reduction. To mitigate the runtime overhead, we further introduce parallelization techniques to decompose a large design into multiple smaller sub-netlists that can be optimized simultaneously. Experimental results show that PIMap achieves promising quality improvement over a set of commonly used benchmarks, including improving the majority of the best-known area and delay records for the EPFL benchmark suite.
    Type of Medium: Online Resource
    ISSN: 1936-7406 , 1936-7414
    URL: Article
    DOI: 10.1145/3268344
    Language: English
    Publisher: Association for Computing Machinery (ACM)
    Publication Date: 2018
    detail.hit.zdb_id: 2418475-5
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