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  • Association for Computing Machinery (ACM)  (3)
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  • Association for Computing Machinery (ACM)  (3)
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  • 1
    Online Resource
    Online Resource
    Compiler Optimization for Reducing Leakage Power in Multithread BSP Programs
    Association for Computing Machinery (ACM) ; 2014
    In:  ACM Transactions on Design Automation of Electronic Systems Vol. 20, No. 1 ( 2014-11-18), p. 1-34
    Details
    In: ACM Transactions on Design Automation of Electronic Systems, Association for Computing Machinery (ACM), Vol. 20, No. 1 ( 2014-11-18), p. 1-34
    Abstract: Multithread programming is widely adopted in novel embedded system applications due to its high performance and flexibility. This article addresses compiler optimization for reducing the power consumption of multithread programs. A traditional compiler employs energy management techniques that analyze component usage in control-flow graphs with a focus on single-thread programs. In this environment the leakage power can be controlled by inserting on and off instructions based on component usage information generated by flow equations. However, these methods cannot be directly extended to a multithread environment due to concurrent execution issues. This article presents a multithread power-gating framework composed of multithread power-gating analysis (MTPGA) and predicated power-gating (PPG) energy management mechanisms for reducing the leakage power when executing multithread programs on simultaneous multithreading (SMT) machines. Our multithread programming model is based on hierarchical bulk-synchronous parallel (BSP) models. Based on a multithread component analysis with dataflow equations, our MTPGA framework estimates the energy usage of multithread programs and inserts PPG operations as power controls for energy management. We performed experiments by incorporating our power optimization framework into SUIF compiler tools and by simulating the energy consumption with a post-estimated SMT simulator based on Wattch toolkits. The experimental results show that the total energy consumption of a system with PPG support and our power optimization method is reduced by an average of 10.09% for BSP programs relative to a system without a power-gating mechanism on leakage contribution set to 30%; and the total energy consumption is reduced by an average of 4.27% on leakage contribution set to 10%. The results demonstrate our mechanisms are effective in reducing the leakage energy of BSP multithread programs.
    Type of Medium: Online Resource
    ISSN: 1084-4309 , 1557-7309
    URL: Article
    DOI: 10.1145/2668119
    Language: English
    Publisher: Association for Computing Machinery (ACM)
    Publication Date: 2014
    detail.hit.zdb_id: 1501152-5
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  • 2
    Online Resource
    Online Resource
    The Design and Experiments of A SID-Based Power-Aware Simulator for Embedded Multicore Systems
    Association for Computing Machinery (ACM) ; 2015
    In:  ACM Transactions on Design Automation of Electronic Systems Vol. 20, No. 2 ( 2015-03-02), p. 1-27
    Details
    In: ACM Transactions on Design Automation of Electronic Systems, Association for Computing Machinery (ACM), Vol. 20, No. 2 ( 2015-03-02), p. 1-27
    Abstract: Embedded multicore systems are playing increasingly important roles in the design of consumer electronics. The objective of such systems is to optimize both performance and power characteristics of mobile devices. However, currently there are no power metrics supporting popular application design platforms (such as SID) that application developers use to develop their applications. This hinders the ability of application developers to optimize power consumption. In this article we present the design and experiments of a SID-based power-aware simulation framework for embedded multicore systems. The proposed power estimation flow includes two phases: IP-level power modeling and power-aware system simulation. The first phase employs PowerMixer IP to construct the power model for the processor IP and other major IPs, while the second phase involves a power abstract interpretation method for summarizing the simulation trace, then, with a CPE module, estimating the power consumption based on the summarized trace information and the input of IP power models. In addition, a Manager component is devised to map each digital signal processor (DSP) component to a host thread and maintain the access to shared resources. The aim is to maintain the simulation performance as the number of simulated DSP components increases. A power-profiling API is also supported that developers of embedded software can use to tune the granularity of power-profiling for a specific code section of the target application. We demonstrate via case studies and experiments how application developers can use our SID-based power simulator for optimizing the power consumption of their applications. We characterize the power consumption of DSP applications with the DSPstone benchmark and discuss how compiler optimization levels with SIMD intrinsics influence the performance and power consumption. A histogram application and an augmented-reality application based on human-face-based RMS (recognition, mining, and synthesis) application are deployed as running examples on multicore systems to demonstrate how our power simulator can be used by developers in the optimization process to illustrate different views of power dissipations of applications.
    Type of Medium: Online Resource
    ISSN: 1084-4309 , 1557-7309
    URL: Article
    DOI: 10.1145/2699834
    Language: English
    Publisher: Association for Computing Machinery (ACM)
    Publication Date: 2015
    detail.hit.zdb_id: 1501152-5
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  • 3
    Online Resource
    Online Resource
    Compilation for compact power-gating controls
    Association for Computing Machinery (ACM) ; 2007
    In:  ACM Transactions on Design Automation of Electronic Systems Vol. 12, No. 4 ( 2007-09), p. 51-
    Details
    In: ACM Transactions on Design Automation of Electronic Systems, Association for Computing Machinery (ACM), Vol. 12, No. 4 ( 2007-09), p. 51-
    Abstract: Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies due to the continuing size reductions and increasing speeds of transistors. Recent studies have attempted to reduce leakage power using integrated architecture and compiler power-gating mechanisms. This approach involves compilers inserting instructions into programs to shut down and wake up components, as appropriate. While early studies showed this approach to be effective, there are concerns about the large amount of power-control instructions being added to programs due to the increasing amount of components equipped with power-gating controls in SoC design platforms. In this article we present a sink-n-hoist framework for a compiler to generate balanced scheduling of power-gating instructions. Our solution attempts to merge several power-gating instructions into a single compound instruction, thereby reducing the amount of power-gating instructions issued. We performed experiments by incorporating our compiler analysis and scheduling policies into SUIF compiler tools and by simulating the energy consumption using Wattch toolkits. The experimental results demonstrate that our mechanisms are effective in reducing the amount of power-gating instructions while further reducing leakage power compared to previous methods.
    Type of Medium: Online Resource
    ISSN: 1084-4309 , 1557-7309
    URL: Article
    DOI: 10.1145/1278349.1278364
    Language: English
    Publisher: Association for Computing Machinery (ACM)
    Publication Date: 2007
    detail.hit.zdb_id: 1501152-5
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