In:
Applied Physics Letters, AIP Publishing, Vol. 101, No. 23 ( 2012-12-03)
Abstract:
We studied the charge loss mechanism of a non-volatile memory device with vanadium silicide (V3Si) nano-particles (NPs) embedded in a silicon dioxide dielectric layer. To fabricate the memory device, V3Si NPs with an average size of 4–6 nm were formed between the tunnel and control oxide layers by a thin film deposition and a post-annealing process at 800 °C for 5 s. Using the gate structure containing the V3Si NPs, a flash memory structure was fabricated with a channel length and width of 5 μm. This device maintained the memory window at about 1 V after 104 s when program/erase voltages of ±9 V were applied for 1 s. The activation energies of the V3Si NP memory devices with charge loss rates of 10%, 15%, 20%, and 25% were approximately 0.16, 0.24, 0.35, and 0.50 eV, respectively. The charge loss mechanism can be attributed to direct tunneling as a result of the NPs associating with the interface trap in the tunneling oxide, the Pool-Frenkel current, and the oxide defect.
Type of Medium:
Online Resource
ISSN:
0003-6951
,
1077-3118
Language:
English
Publisher:
AIP Publishing
Publication Date:
2012
detail.hit.zdb_id:
211245-0
detail.hit.zdb_id:
1469436-0
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