In:
Advanced Materials Research, Trans Tech Publications, Ltd., Vol. 756-759 ( 2013-9), p. 205-208
Abstract:
In this paper, we present an 8-bit 5 Gsample/s time-interleaved analog-to-digital converter (TI ADC). A 4-phase low jitter clock is designed to control four 1.25 Gsample/s sub-ADCs which is implemented using folding and interpolating architecture. Digital calibration is used to adjust the offset error and gain error of sub-ADCs. Meanwhile, serial peripheral interface (SPI) is adopted to adjust mismatch of gain and sample time between sub-ADCs. The whole TI ADC is designed using a 0.18m SiGe BiCMOS process. The whole ADC has a SNR of about 45 dB at the input frequency of 495 MHZ and an equivalent ENOB of 7.2 bits.
Type of Medium:
Online Resource
ISSN:
1662-8985
DOI:
10.4028/www.scientific.net/AMR.756-759
DOI:
10.4028/www.scientific.net/AMR.756-759.205
Language:
Unknown
Publisher:
Trans Tech Publications, Ltd.
Publication Date:
2013
detail.hit.zdb_id:
2265002-7
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