In:
ACM SIGMICRO Newsletter, Association for Computing Machinery (ACM), Vol. 16, No. 4 ( 1985-12), p. 109-116
Abstract:
HPS is a new model for a high performance microarchitecture which is targeted for implementing very dissimilar ISP architectures. It derives its performance from executing the operations within a restricted window of a program out-of-order, asynchronously, and concurrently whenever possible. Before the model can be reduced to an effective working implementation of a particular target architecture, several issues need to be resolved. This paper discusses these issues, both in general and in the context of architectures with specific characteristics.
Type of Medium:
Online Resource
ISSN:
1050-916X
Language:
English
Publisher:
Association for Computing Machinery (ACM)
Publication Date:
1985
detail.hit.zdb_id:
243814-8
detail.hit.zdb_id:
2089076-X
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