In:
Japanese Journal of Applied Physics, IOP Publishing, Vol. 60, No. 6 ( 2021-06-01), p. 060901-
Abstract:
The threshold voltage shift in NO-annealed 4H-SiC MOSFETs during negative gate bias stress was investigated with a fast on-the-fly method for p-channel devices while considering the stress–time dependence of the slope of the drain current–gate voltage characteristics. With the proposed method, the threshold voltage shift was accurately measured over a wide time range from hundreds of nanoseconds. The negative threshold voltage shift exhibited power-law time dependence at room temperature and logarithmic time dependence at 423 K, suggesting that interface trap generation is observable at room temperature and thermally-assisted hole trapping in SiO 2 dominates at high temperatures.
Type of Medium:
Online Resource
ISSN:
0021-4922
,
1347-4065
DOI:
10.35848/1347-4065/abff38
Language:
Unknown
Publisher:
IOP Publishing
Publication Date:
2021
detail.hit.zdb_id:
218223-3
detail.hit.zdb_id:
797294-5
detail.hit.zdb_id:
2006801-3
detail.hit.zdb_id:
797295-7
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