In:
Japanese Journal of Applied Physics, IOP Publishing
Abstract:
1.2 kV silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with buffered oxide, which are developed to reduce the gate-drain charge (Q GD ), have the problem that the electric field is crowded at the corners of the buffered oxide. In this paper, 1.2 kV SiC MOSFETs with tapered buffer oxide are proposed to suppress the electric field crowding effect. The device with tapered buffer oxide having an angle of 40° demonstrates maximum electric field at the gate oxide in the off-state (E ox,max ) of 1.87 MV/cm, achieving a 13.4 % reduction compared to the device with conventional structure. Additionally, it is verified that the output characteristics of 1.2 kV SiC MOSFETs can be improved by applying tapered buffer oxide. This is because the junction field effect transistor (JFET) region can be designed with high concentration through the suppression of the electric field of the tapered buffer oxide.
Type of Medium:
Online Resource
ISSN:
0021-4922
,
1347-4065
DOI:
10.35848/1347-4065/acff2f
Language:
Unknown
Publisher:
IOP Publishing
Publication Date:
2023
detail.hit.zdb_id:
218223-3
detail.hit.zdb_id:
797294-5
detail.hit.zdb_id:
2006801-3
detail.hit.zdb_id:
797295-7
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