In:
Semiconductor Science and Technology, IOP Publishing, Vol. 37, No. 3 ( 2022-03-01), p. 035019-
Abstract:
Junctionless complementary field effect transistor (JL-CFET) is an emerging device that needs a small layout area and low fabrication cost. However, in order for the JL-CFET to be adopted for low power applications, two main constraints need to be overcome: (a) a high work function of metal gate and (b) a low drain current. In this work, an optimal device design is proposed to overcome those problems, by analyzing various performance metrics, such as on-state drive current, subthreshold swing, drain induced barrier lowering, propagation delay time, and ring oscillator’s oscillation frequency, which are extracted from various structures of JL-CFET. In addition, the negative capacitance effect in JL-CFET is examined to address the limit from device structures.
Type of Medium:
Online Resource
ISSN:
0268-1242
,
1361-6641
DOI:
10.1088/1361-6641/ac41e6
Language:
Unknown
Publisher:
IOP Publishing
Publication Date:
2022
detail.hit.zdb_id:
54647-1
detail.hit.zdb_id:
1361285-2
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