In:
Japanese Journal of Applied Physics, IOP Publishing, Vol. 53, No. 4S ( 2014-04-01), p. 04EA04-
Abstract:
We report on aggressively scaled replacement metal gate, high- k last (RMG-HKL) planar and multi-gate fin field-effect transistor (FinFET) devices, systematically investigating the impact of post high- k deposition thermal (PDA) and plasma (SF 6 ) treatments on device characteristics, and providing a deeper insight into underlying degradation mechanisms. We demonstrate that: 1) substantially reduced gate leakage ( J G ) and noise can be obtained for both type of devices with PDA and F incorporation in the gate stack by SF 6 , without equivalent oxide thickness (EOT) penalty; 2) SF 6 enables improved mobility and reduced interface trapped charge density ( N it ) down to narrower fin devices [fin width ( W Fin ) ≥ 5 nm], mitigating the impact of fin patterning and fin sidewall crystal orientations, while allowing a simplified dual-effective work function (EWF) CMOS scheme suitable for both device architectures; 3) PDA yields smaller, in absolute values, PMOS threshold voltage | V T |, and substantially improved reliability behavior due to reduction of bulk defects.
Type of Medium:
Online Resource
ISSN:
0021-4922
,
1347-4065
DOI:
10.7567/JJAP.53.04EA04
Language:
Unknown
Publisher:
IOP Publishing
Publication Date:
2014
detail.hit.zdb_id:
218223-3
detail.hit.zdb_id:
797294-5
detail.hit.zdb_id:
2006801-3
detail.hit.zdb_id:
797295-7
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