GLORIA

GEOMAR Library Ocean Research Information Access

Your email was sent successfully. Check your inbox.

An error occurred while sending the email. Please try again.

Proceed reservation?

Export
  • 1
    In: ECS Transactions, The Electrochemical Society, Vol. 69, No. 5 ( 2015-09-08), p. 9-13
    Abstract: We report on electrical characteristics of HfO 2 /Al 2 O 3 gate dielectric on InGaAs as a function of Al 2 O 3 ALD cycles. We also investigate the effect of a NH 3 treatment in a 300mm PEALD chamber equipped with a capacitive plasma. It is shown that 8 Al 2 O 3 cycles are required to achieve a high level capacitance (1.75μF/cm²) and an interface trap density (D it ) around 6×10 12 cm -² eV -1 . The NH 3 plasma treatment through an Al 2 O 3 layer is able to integrate nitrogen at the InGaAs interface and to form an oxynitride GaO x N y .without deterioration of the C-V characteristics.
    Type of Medium: Online Resource
    ISSN: 1938-5862 , 1938-6737
    Language: Unknown
    Publisher: The Electrochemical Society
    Publication Date: 2015
    Location Call Number Limitation Availability
    BibTip Others were also interested in ...
  • 2
    In: ECS Transactions, The Electrochemical Society, Vol. 3, No. 7 ( 2006-10-20), p. 355-363
    Abstract: This paper reviews the concept, manufacturing process and electrical characteristics of a novel self-aligned SiGeC HBT structure suitable for thin-film SOI substrates. It then describes the integration of this device into 130nm SOI CMOS technology, and presents early results on the development of a complementary pnp HBT.
    Type of Medium: Online Resource
    ISSN: 1938-5862 , 1938-6737
    Language: Unknown
    Publisher: The Electrochemical Society
    Publication Date: 2006
    Location Call Number Limitation Availability
    BibTip Others were also interested in ...
  • 3
    In: ECS Transactions, The Electrochemical Society, Vol. 64, No. 5 ( 2014-08-14), p. 35-48
    Abstract: Bulk silicon device technologies are reaching fundamental scaling limitations. The 28 nm and 22 nm technology nodes have seen the introduction of Ultra-Thin Body and Buried Oxide Fully Depleted SOI (UTBB-FDSOI) devices and FinFETs, respectively. Fully Depleted transistor technologies are mandatory to suppress short channel effects. Today, all major research and development alliances state that the silicon and its Fully Depleted transistor technologies have the potential to address roadmap requirements down to the 10nm node. Innovations will be necessary for lower, more advanced node (under 10nm). Specifications are to continue to ensure a good electrostatic control while providing excellent electrical performance. To meet these demands, several research areas (substrate engineering as well as multiple gate devices and 3D integration) will be involved in integrated circuit fabrication. This paper reports our latest achievements in SOI-type bonded substrates for advanced technology nodes.
    Type of Medium: Online Resource
    ISSN: 1938-5862 , 1938-6737
    Language: Unknown
    Publisher: The Electrochemical Society
    Publication Date: 2014
    Location Call Number Limitation Availability
    BibTip Others were also interested in ...
  • 4
    In: ECS Meeting Abstracts, The Electrochemical Society, Vol. MA2015-02, No. 18 ( 2015-07-07), p. 813-813
    Abstract: The achievement of a good high-k oxide/InGaAs interface quality is a key challenge to obtain high performance MOSFET. Associating Al 2 O 3 and HfO 2 in a bilayer oxide is interesting to benefit from the good interface quality obtained with Al 2 O 3 and the better electrostatic control achievable with HfO 2 . Furthermore, some recent work evidenced the reduction of the interface trap density (D it ) by using a plasma nitridation process [1]. For the first time, we evaluated the passivation properties of a Al 2 O 3 /HfO 2 bilayer and a nitridation treatment on industrial equipment compatible with 300 mm Si wafers. First, we investigated the number of Al 2 O 3 ALD cycles required to obtain a good interface. Second, we evaluated the effect of a nitridation treatment on the Al 2 O 3 /InGaAs interface properties performed on a 300 mm capacitive plasma tool. MOSCAP structures were fabricated on a 27 nm thick In 0.53 Ga 0.47 As layer grown on InP substrates. The samples were cleaned in a NH 4 OH solution (4%) for 1 min at room temperature and rinsed in deionized water. Then, Al 2 O 3 and HfO 2 films were deposited in a ALD chamber at 300°C with trimethylaluminium (TMA), Hafnium tetrachloride (HfCl 4 ) and H 2 O as precursors. The ALD cycle numbers for Al 2 O 3 were 0, 3, 5, 8 and 10 and 32 for HfO 2 . A post-deposition annealing was carried out at 370°C for 30 min in N 2 ambient. For the nitridation study, one InGaAs sample was directly treated with a NH 3 plasma for 120 s at 50W and two samples were treated with a NH 3 plasma or a N 2 plasma for 120 s at 50W after the deposition of Al 2 O 3 (10 ALD cycles) to prevent damages on the III-V layer. After the plasma treatment, Al 2 O 3 was again deposited to reach a 8 nm-thick layer for electrical characterization. Ni/Au gate electrode was deposited through a shadow mask by e-beam evaporation. The sample without Al 2 O 3  (Fig1.a) presents distorted profiles, especially at 10 kHz, sign of a poor InGaAs/HfO 2 interface quality. Depositing three Al 2 O 3  cycles (fig.1.b) allows a limited improvement of the characteristics. The dispersion in accumulation of the 10 and 30 kHz curves is reduced but no clear accumulation plateau can be seen. From 5 to 10 cycles, samples (c-e), the situation is significantly improved with a clear accumulation regime. The interface trap densities (D it ) were estimated using the conductance method [2] and were found equal to ~11, 6.1 and 5.5 ×10 12 cm -2 eV -1 for the 5, 8 and 10 cycles samples respectively. A clear improvement is obtained from 5 to 8 cycles while only a slight improvement is obtained from 8 to 10 cycles. Compare to the Al 2 O 3 /InGaAs capacitor (fig.1.f), the best compromise between low D it and high level capacitance appears to be 8 Al 2 O 3  cycles. Wide frequency dispersion in accumulation can be seen after NH 3 treatment without the Al 2 O 3  protection (fig.2c) due to border traps in the dielectric. The plasma treatment prior to the dielectric deposition induces defects at the beginning of the nucleation. This dispersion is reduced when the treatment is implemented through an Al 2 O 3  layer (fig.2b and d). N 2 plasma reduces the capacitance whereas NH 3 plasma does not deteriorate the C-V characteristics and keeps the same capacitance as the sample without nitridation. According to XPS analysis, N is clearly detected after plasma treatment. The N1s peak can be divided into two components, N1s A at 399.0 eV and N1s B at 397.9 eV. The N1s A component has been attributed to N-O bonds, and N1s B to N-Ga bonds [3]. Residual As oxides are reduced with NH 3 (fig. 3e and f) but no As nitride is evidenced. After plasma treatment, the Ga 3+ peak increases significantly (fig.3c and d), because of N incorporation at the interface. The Ga 3+ component can be attributed to Ga-O and Ga-N bonds resulting in an oxynitride formation [1]. In conclusion, Al 2 O 3 /HfO 2 bilayer was optimized on a 300 mm equipment to achieve low D it and high level capacitance (1.75 µF/cm²). NH3 nitridation process performed on a 300 mm capacitive plasma tool integrates nitrogen at the InGaAs surface without deterioration of the C-V characteristics. Low D it is estimated at 2×10 12 cm -2 eV -1 at room temperature after NH 3 plasma which is close to the value shown in [1] obtained with an ECR plasma. Measurements at lower temperature will further explain the D it energy distribution. [1] T. Hoshii, J. Appl. Phys., vol. 112, no. 7, p. 073702, 2012. [2] R. Engel-Herbert, Appl. Phys. Lett., vol. 97, no. 6, p. 062905, 2010. [3] T. S. Lay, J. Vac. Sci. Technol. B Microelectron. Nanom. Struct., vol. 22, no. 3, p. 1491, 2004. Figure 1
    Type of Medium: Online Resource
    ISSN: 2151-2043
    Language: Unknown
    Publisher: The Electrochemical Society
    Publication Date: 2015
    detail.hit.zdb_id: 2438749-6
    Location Call Number Limitation Availability
    BibTip Others were also interested in ...
  • 5
    In: ECS Meeting Abstracts, The Electrochemical Society, Vol. MA2014-02, No. 34 ( 2014-08-05), p. 1720-1720
    Abstract: Bulk silicon device technologies are reaching fundamental scaling limitations. The 28nm and 22nm technology nodes have seen the introduction of Ultra-Thin Body and Buried Oxide Fully Depleted SOI (UTBB-FDSOI) [1] and FinFETs [2] , respectively. Fully Depleted transistor technologies are mandatory to suppress short channel effects. Today, all major research and development alliances carry the message that the silicon and its Fully Depleted transistor technologies have the potential to address roadmap requirements down to 10nm node. Innovations will be necessary for lowest node (under 10nm). Specifications are to continue to ensure a good electrostatic control while providing excellent electrical performance. To meet these demands, several research areas (substrate engineering as well as multiple gate devices and 3D integration) will be involved in integrated circuit fabrication (Fig. 1). High mobility materials are expected to replace silicon as the channel material: attention has been focused recently on the III-V and the Ge materials (Fig.1). Indeed, III-V semiconductors (such as GaAs, InP, InGaAs and InAs) have extremely high electron mobility and low electron effective mass and Ge has extremely high hole mobility and low hole effective mass [3]. In order to avoid short channel effects, these “new” materials have to be transferred as thin layers on buried oxide layers. SOI substrates are fabricated using the Smart Cut TM technology. This process, based on hydrogen implantation and wafer bonding, made it possible to transfer a thin layer of crystalline material from a donor substrate to another substrate. This versatile technique for thin layer transfer enables the fabrication of hetero-substrates with a large choice for the crystalline superficial layers, the buried layers and even the handle substrates (Fig. 2). For More Moore applications, this leaves the freedom to transfer Ge or III-V thin layer on an optimized buried oxide layer. In this paper, we will present our latest work on advanced SOI substrates for sub-28nm technology node and on novel “on insulator” substrates for sub-10nm node. We developed GeOI (Fig. 3) and InGaAs-OI (Fig. 4) substrates in 300mm. It is otherwise possible, thanks to low temperature direct bonding, to combine 3D CMOS integration (thereby increasing transistor density) and high mobility channel devices : a monolithic and vertical co-integration of GeOI pMOSFETs stacked on SOI nMOSFETs [4] or a III-V-OI nMOSFETs stacked on a SiGeOI pMOSFETs [5] have already been demonstrated with functional inverters and SRAM cells. Acknowledgments: the authors acknowledge financial support from the European Commission via the FP7-COMPOSE3 and from the French Government's Investissement d'Avenir program (eXact projet). [1] J. Hartmann, FDSOI workshop, 2012 [2] C. Auth, VLSI-T, 2012 [3] S. Takagi, IEEE TED, 2008 [4] P. Batude, VLSI 2009 [5] T. Irisawa, VLSI, 2013.
    Type of Medium: Online Resource
    ISSN: 2151-2043
    Language: Unknown
    Publisher: The Electrochemical Society
    Publication Date: 2014
    detail.hit.zdb_id: 2438749-6
    Location Call Number Limitation Availability
    BibTip Others were also interested in ...
Close ⊗
This website uses cookies and the analysis tool Matomo. More information can be found here...